The following changes since commit 80db93b2b88f9b3ed8927ae7ac74ca30e643a83e:
Merge tag 'pull-aspeed-20250526' of https://github.com/legoater/qemu into staging (2025-05-26 10:16:59 -0400) are available in the Git repository at: https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20250528 for you to fetch changes up to 5c2891601ccdaa41427187ef95bc25c828b355e4: accel/tcg: Assert TCGCPUOps.pointer_wrap is set (2025-05-28 08:08:48 +0100) ---------------------------------------------------------------- accel/tcg: Fix atomic_mmu_lookup vs TLB_FORCE_SLOW linux-user: implement pgid field of /proc/self/stat target/sh4: Use MO_ALIGN for system UNALIGN() target/microblaze: Use TARGET_LONG_BITS == 32 for system mode accel/tcg: Add TCGCPUOps.pointer_wrap target/*: Populate TCGCPUOps.pointer_wrap ---------------------------------------------------------------- Andreas Schwab (1): linux-user: implement pgid field of /proc/self/stat Pierrick Bouvier (1): system/main: comment lock rationale Richard Henderson (26): accel/tcg: Fix atomic_mmu_lookup vs TLB_FORCE_SLOW target/microblaze: Split out mb_unaligned_access_internal target/microblaze: Introduce helper_unaligned_access target/microblaze: Split out mb_transaction_failed_internal target/microblaze: Implement extended address load/store out of line target/microblaze: Use uint64_t for CPUMBState.ear target/microblaze: Use TCGv_i64 for compute_ldst_addr_ea target/microblaze: Fix printf format in mmu_translate target/microblaze: Use TARGET_LONG_BITS == 32 for system mode target/microblaze: Drop DisasContext.r0 target/microblaze: Simplify compute_ldst_addr_type{a,b} tcg: Drop TCGContext.tlb_dyn_max_bits tcg: Drop TCGContext.page_{mask,bits} target/sh4: Use MO_ALIGN for system UNALIGN() accel/tcg: Add TCGCPUOps.pointer_wrap target: Use cpu_pointer_wrap_notreached for strict align targets target: Use cpu_pointer_wrap_uint32 for 32-bit targets target/arm: Fill in TCGCPUOps.pointer_wrap target/i386: Fill in TCGCPUOps.pointer_wrap target/loongarch: Fill in TCGCPUOps.pointer_wrap target/mips: Fill in TCGCPUOps.pointer_wrap target/ppc: Fill in TCGCPUOps.pointer_wrap target/riscv: Fill in TCGCPUOps.pointer_wrap target/s390x: Fill in TCGCPUOps.pointer_wrap target/sparc: Fill in TCGCPUOps.pointer_wrap accel/tcg: Assert TCGCPUOps.pointer_wrap is set include/accel/tcg/cpu-ops.h | 13 ++++ include/tcg/tcg.h | 4 - target/microblaze/cpu.h | 2 +- target/microblaze/helper.h | 22 ++++-- accel/tcg/cpu-exec.c | 1 + accel/tcg/cputlb.c | 37 +++++++-- accel/tcg/translate-all.c | 6 -- linux-user/syscall.c | 3 + system/main.c | 13 ++++ target/alpha/cpu.c | 1 + target/arm/cpu.c | 24 ++++++ target/arm/tcg/cpu-v7m.c | 1 + target/avr/cpu.c | 6 ++ target/hppa/cpu.c | 1 + target/i386/tcg/tcg-cpu.c | 7 ++ target/loongarch/cpu.c | 7 ++ target/m68k/cpu.c | 1 + target/microblaze/cpu.c | 1 + target/microblaze/helper.c | 71 ++++++++++------- target/microblaze/mmu.c | 3 +- target/microblaze/op_helper.c | 110 +++++++++++++++++++------- target/microblaze/translate.c | 128 ++++++++++++++++--------------- target/mips/cpu.c | 9 +++ target/openrisc/cpu.c | 1 + target/ppc/cpu_init.c | 7 ++ target/riscv/tcg/tcg-cpu.c | 26 +++++++ target/rx/cpu.c | 1 + target/s390x/cpu.c | 9 +++ target/sh4/cpu.c | 1 + target/sh4/translate.c | 2 +- target/sparc/cpu.c | 13 ++++ target/tricore/cpu.c | 1 + target/xtensa/cpu.c | 1 + tcg/perf.c | 2 +- tcg/tcg-op-ldst.c | 3 +- tcg/tcg.c | 1 + configs/targets/microblaze-softmmu.mak | 4 +- configs/targets/microblazeel-softmmu.mak | 4 +- tcg/aarch64/tcg-target.c.inc | 10 +-- tcg/arm/tcg-target.c.inc | 10 +-- tcg/i386/tcg-target.c.inc | 10 +-- tcg/loongarch64/tcg-target.c.inc | 4 +- tcg/mips/tcg-target.c.inc | 6 +- tcg/ppc/tcg-target.c.inc | 14 ++-- tcg/riscv/tcg-target.c.inc | 4 +- tcg/s390x/tcg-target.c.inc | 4 +- tcg/sparc64/tcg-target.c.inc | 4 +- 47 files changed, 427 insertions(+), 186 deletions(-)
