On 5/15/25 08:05, Alistair Francis wrote:
On Mon, May 12, 2025 at 7:53 PM Paolo Bonzini <[email protected]> wrote:Same as v4, with suggestion from Richard to avoid parentheses---which also fixes the issue with kvm-cpu.c reported by Daniel Barboza. KVM/RISC-V is now covered in CI and passes with this version. Paolo Paolo Bonzini (26): target/riscv: assert argument to set_satp_mode_max_supported is valid target/riscv: cpu: store max SATP mode as a single integer target/riscv: update max_satp_mode based on QOM properties target/riscv: remove supported from RISCVSATPMap target/riscv: move satp_mode.{map,init} out of CPUConfig target/riscv: introduce RISCVCPUDef target/riscv: store RISCVCPUDef struct directly in the class target/riscv: merge riscv_cpu_class_init with the class_base function target/riscv: move RISCVCPUConfig fields to a header file target/riscv: include default value in cpu_cfg_fields.h.inc target/riscv: add more RISCVCPUDef fields target/riscv: convert abstract CPU classes to RISCVCPUDef target/riscv: convert profile CPU models to RISCVCPUDef target/riscv: convert bare CPU models to RISCVCPUDef target/riscv: convert dynamic CPU models to RISCVCPUDef target/riscv: convert SiFive E CPU models to RISCVCPUDef target/riscv: convert ibex CPU models to RISCVCPUDef target/riscv: convert SiFive U models to RISCVCPUDef target/riscv: th: make CSR insertion test a bit more intuitive target/riscv: generalize custom CSR functionality target/riscv: convert TT C906 to RISCVCPUDef target/riscv: convert TT Ascalon to RISCVCPUDef target/riscv: convert Ventana V1 to RISCVCPUDef target/riscv: convert Xiangshan Nanhu to RISCVCPUDef target/riscv: remove .instance_post_init qom: reverse order of instance_post_init callsThis doesn't seem to have made it through to Patchew for some reason: https://patchew.org/search?q=SATP+mode+and+CPU+definition+overhaul
Yes, mailman decided to unsubscribe Patchew on Friday and I was only able to resubscribe on Monday. :/
Paolo
