From: Kane-Chen-AS <[email protected]> Dear reviewers,
This series introduces the ASPEED OTP (One-Time Programmable) memory model and connects it to the SBC controller and AST10x0/AST2600 SoCs. The OTP model supports irreversible bit programming, file-backed content, and tracepoints for program conflict debugging. Patch 2 links the OTP device to the SBC controller and enables command handling. Patch 3 exposes the machine parameter and updates the SoC tree. Any feedback or suggestions are appreciated! Thanks, Kane --- ChangeLog --------- v4: - Replaces blockdev backend with memory-mapped AddressSpace access - Switches from `-drive` CLI option to `otpmem` machine parameter - Restructures the OTP device under the SBC in the QOM tree v3: - Minor fixes and refinements on top of v2 content v2: - Separated the OTP memory into a standalone QEMU device (`aspeed.otpmem`) - Replaced ad-hoc file handling with standard `-drive` backend integration - Linked OTP to SBC via QOM property for cleaner abstraction - Improved memory bounds checking and irreversible programming logic v1: - Embedded OTP logic in the SBC model and created the backing file internally. --- Kane-Chen-AS (3): hw/misc/aspeed_otp: Add ASPEED OTP memory device model hw/misc/aspeed_sbc: Connect ASPEED OTP memory device to SBC controller hw/arm: Integrate ASPEED OTP memory into AST10x0 and AST2600 SoCs hw/arm/aspeed.c | 20 ++++ hw/arm/aspeed_ast10x0.c | 2 +- hw/arm/aspeed_ast2600.c | 2 +- hw/misc/aspeed_otpmem.c | 198 ++++++++++++++++++++++++++++++++ hw/misc/aspeed_sbc.c | 197 +++++++++++++++++++++++++++++++ hw/misc/meson.build | 1 + hw/misc/trace-events | 10 ++ include/hw/misc/aspeed_otpmem.h | 39 +++++++ include/hw/misc/aspeed_sbc.h | 6 + 9 files changed, 473 insertions(+), 2 deletions(-) create mode 100644 hw/misc/aspeed_otpmem.c create mode 100644 include/hw/misc/aspeed_otpmem.h -- 2.43.0
