On 28/4/25 14:17, Paolo Bonzini wrote:
On Mon, Apr 28, 2025 at 1:50 PM Daniel Henrique Barboza
<[email protected]> wrote:
On 4/28/25 4:34 AM, Paolo Bonzini wrote:
Prepare for adding more fields to RISCVCPUDef and reading them in
riscv_cpu_init: instead of storing the misa_mxl_max field in
RISCVCPUClass, ensure that there's always a valid RISCVCPUDef struct
and go through it.
Reviewed-by: Alistair Francis <[email protected]>
Signed-off-by: Paolo Bonzini <[email protected]>
---
target/riscv/cpu.h | 2 +-
hw/riscv/boot.c | 2 +-
target/riscv/cpu.c | 23 ++++++++++++++++++-----
target/riscv/gdbstub.c | 6 +++---
target/riscv/kvm/kvm-cpu.c | 21 +++++++++------------
target/riscv/machine.c | 2 +-
target/riscv/tcg/tcg-cpu.c | 10 +++++-----
target/riscv/translate.c | 2 +-
8 files changed, 39 insertions(+), 29 deletions(-)
Are we sure this patch compiles?
No, you're right; I was not aware that RISC-V KVM is not covered by
CI. I'm sorry.
I remember doing it and Daniel reviewed it...:
https://lore.kernel.org/qemu-devel/[email protected]/
I suppose the shame is on me for not insisting getting it merged,
wasting my own time.
