Richard Henderson <[email protected]> writes:
> On 2/26/25 06:03, Alex Bennée wrote:
>> Clang complains:
>> clang -O2 -m64 -mcx16
>> /home/alex/lsrc/qemu.git/tests/tcg/i386/test-i386-adcox.c -o
>> test-i386-adcox -static
>> /home/alex/lsrc/qemu.git/tests/tcg/i386/test-i386-adcox.c:32:26: error:
>> invalid input constraint '0' in asm
>> : "r" ((REG)-1), "0" (flags), "1" (out_adcx), "2" (out_adox));
>> ^
>> /home/alex/lsrc/qemu.git/tests/tcg/i386/test-i386-adcox.c:57:26: error:
>> invalid input constraint '0' in asm
>> : "r" ((REG)-1), "0" (flags), "1" (out_adcx), "2" (out_adox));
>> ^
>> 2 errors generated.
>> Pointing out a numbered input constraint can't point to a read/write
>> output [1]. Convert to a read-only input constraint to allow this.
>> [1]
>> https://lists.llvm.org/pipermail/cfe-commits/Week-of-Mon-20101101/036036.html
>> Signed-off-by: Alex Bennée <[email protected]>
>> Suggested-by: Daniel P. Berrangé <[email protected]>
>> ---
>> tests/tcg/i386/test-i386-adcox.c | 4 ++--
>> 1 file changed, 2 insertions(+), 2 deletions(-)
>> diff --git a/tests/tcg/i386/test-i386-adcox.c
>> b/tests/tcg/i386/test-i386-adcox.c
>> index 16169efff8..b56dbc00f2 100644
>> --- a/tests/tcg/i386/test-i386-adcox.c
>> +++ b/tests/tcg/i386/test-i386-adcox.c
>> @@ -28,7 +28,7 @@ void test_adox_adcx(uint32_t in_c, uint32_t in_o, REG
>> adcx_operand, REG adox_ope
>> "adox %3, %2;"
>> "adcx %3, %1;"
>> "pushf; pop %0"
>> - : "+r" (flags), "+r" (out_adcx), "+r" (out_adox)
>> + : "=r"(flags), "=r"(out_adcx), "=r"(out_adox)
>> : "r" ((REG)-1), "0" (flags), "1" (out_adcx), "2" (out_adox));
>
> Alternately, drop all of the matching constraints as redundant.
> That's what "+r" does, anyway.
You mean like this:
asm("push %0; popf;"
"adox %3, %2;"
"adcx %3, %1;"
"pushf; pop %0"
: "+r"(flags), "+r"(out_adcx), "+r"(out_adox));
Because that breaks the test:
test-i386-adcox:
/home/alex/lsrc/qemu.git/tests/tcg/i386/test-i386-adcox.c:33: test_adox_adcx:
Assertion `out_adcx == in_c + adcx_operand - 1' failed.
>
>
> r~
--
Alex Bennée
Virtualisation Tech Lead @ Linaro
