> > > #define smp_wmb() asm volatile("eieio" ::: "memory")
> > > +#define smp_mb() asm volatile("eieio" ::: "memory")
> >
> > smp_mb() is hwsync under PPC, but I would just trust GCC.
>
> I assume you mean 'lwsync', no such thing as 'hwsync', afaik. And I
> assume you're talking about the kernel here.
I meant 'sync'. 'lwsync' is only good as a read memory barrier.
> So, the situation in qemu is different from in the kernel, because as
> far as I know there's no case in qemu where we need to synchronize
> cacheable stores with non-cacheable (I/O) stores. eieio won't do
> that, but it will order cacheable stores w.r.t. other cacheable
> stores. I think __sync_synchronize() will be a 'sync', the most
> heavyweight memory barrier on ppc.
Yes.
Paolo
