Hi, In this new version, in patch 2, we're using the address 'size' val from riscv_cpu_tlb_fill() instead of infering it from the CPU XLEN.
No other changes made. Patches based on master. Changes from v2: - patch 2: - use 'size' instead of infering wp_len using the CPU XLEN - v2 link: https://lore.kernel.org/qemu-riscv/20250120204910.1317013-1-dbarb...@ventanamicro.com/ Daniel Henrique Barboza (2): target/riscv/debug.c: use wp size = 4 for 32-bit CPUs target/riscv: throw debug exception before page fault target/riscv/cpu_helper.c | 18 ++++++++++++++++++ target/riscv/debug.c | 6 ++++-- 2 files changed, 22 insertions(+), 2 deletions(-) -- 2.47.1
