Hello,
In this revision two new commits are added to address multi chip SPI issues.
Updates in V5:
1. Use of PnvXferBuffer results in a additonal process overhead due to
frequent dynamic allocations and hence use an existing Fifo8 buffer.
2. Use a local variable seq_index and use it with in while loop instead
of repeatedly calling get_seq_index() and make sure s->seq_op doesn't
overrun when seq_index is incremented.
3. Unique bus names are created for each controller in a socket so that
responders are attched to correct SPI controllers via CLI.
4. Enforce a limit on number RDR match failures so that SPI controller
doesn't get caught in an infinite execution loop querying the responder
for RDR match.
Tested:
passed make check and make check-avocado
Chalapathi V (4):
hw/ssi/pnv_spi: Replace PnvXferBuffer with Fifo8 structure
hw/ssi/pnv_spi: Coverity CID 1558827: Use local var seq_index instead
of get_seq_index().
hw/ssi/pnv_spi: Make bus names distinct for each controllers of a
socket
hw/ssi/pnv_spi: Put a limit to RDR match failures
include/hw/ssi/pnv_spi.h | 6 +-
hw/ppc/pnv.c | 2 +
hw/ssi/pnv_spi.c | 336 ++++++++++++-----------------
tests/qtest/pnv-spi-seeprom-test.c | 2 +-
4 files changed, 143 insertions(+), 203 deletions(-)
--
2.39.5
