The openrisc little-endian control is in a control register: SR[LEE] (which we do not implement at present).
These devices are only used by the OpenRISC target, which is only built as big-endian. Therefore the DEVICE_NATIVE_ENDIAN definition expand to DEVICE_BIG_ENDIAN (besides, the DEVICE_LITTLE_ENDIAN case isn't tested). Simplify directly using DEVICE_BIG_ENDIAN. Signed-off-by: Philippe Mathieu-Daudé <[email protected]> Reviewed-by: Richard Henderson <[email protected]> Reviewed-by: Thomas Huth <[email protected]> Message-Id: <[email protected]> --- hw/openrisc/openrisc_sim.c | 2 +- hw/openrisc/virt.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/openrisc/openrisc_sim.c b/hw/openrisc/openrisc_sim.c index 87f9cbc3001..e0da4067ba3 100644 --- a/hw/openrisc/openrisc_sim.c +++ b/hw/openrisc/openrisc_sim.c @@ -266,7 +266,7 @@ static void openrisc_sim_serial_init(Or1ksimState *state, hwaddr base, } serial_mm_init(get_system_memory(), base, 0, serial_irq, 115200, serial_hd(uart_idx), - DEVICE_NATIVE_ENDIAN); + DEVICE_BIG_ENDIAN); /* Add device tree node for serial. */ nodename = g_strdup_printf("/serial@%" HWADDR_PRIx, base); diff --git a/hw/openrisc/virt.c b/hw/openrisc/virt.c index 22ae057992e..7b60bf85094 100644 --- a/hw/openrisc/virt.c +++ b/hw/openrisc/virt.c @@ -236,7 +236,7 @@ static void openrisc_virt_serial_init(OR1KVirtState *state, hwaddr base, qemu_irq serial_irq = get_per_cpu_irq(cpus, num_cpus, irq_pin); serial_mm_init(get_system_memory(), base, 0, serial_irq, 115200, - serial_hd(0), DEVICE_NATIVE_ENDIAN); + serial_hd(0), DEVICE_BIG_ENDIAN); /* Add device tree node for serial. */ nodename = g_strdup_printf("/serial@%" HWADDR_PRIx, base); -- 2.47.1
