Bitmap table present_cpu_map is added, it is to allocate logical cpu when CPU object is created. Also present_cpu array is added to get logical cpu from physical cpu id.
Signed-off-by: Bibo Mao <[email protected]> --- hw/intc/loongarch_ipi.c | 24 ++++++++++++++++++++++++ include/hw/intc/loongarch_ipi.h | 6 ++++++ include/hw/loongarch/virt.h | 9 +++++++++ 3 files changed, 39 insertions(+) diff --git a/hw/intc/loongarch_ipi.c b/hw/intc/loongarch_ipi.c index 7ea65bcef3..9296006cf6 100644 --- a/hw/intc/loongarch_ipi.c +++ b/hw/intc/loongarch_ipi.c @@ -8,6 +8,7 @@ #include "qemu/osdep.h" #include "hw/boards.h" #include "qemu/error-report.h" +#include "qapi/error.h" #include "hw/intc/loongarch_ipi.h" #include "target/loongarch/cpu.h" @@ -85,11 +86,33 @@ static void loongarch_cpu_unplug(HotplugHandler *hotplug_dev, } } +static void loongarch_ipi_realize(DeviceState *dev, Error **errp) +{ + LoongarchIPIState *lis = LOONGARCH_IPI(dev); + LoongarchIPIClass *lic = LOONGARCH_IPI_GET_CLASS(dev); + Error *local_err = NULL; + int i; + + lic->parent_realize(dev, &local_err); + if (local_err) { + error_propagate(errp, local_err); + return; + } + + for (i = 0; i < MAX_PHY_ID; i++) { + lis->present_cpu[i] = INVALID_CPU; + } +} + static void loongarch_ipi_class_init(ObjectClass *klass, void *data) { + DeviceClass *dc = DEVICE_CLASS(klass); LoongsonIPICommonClass *licc = LOONGSON_IPI_COMMON_CLASS(klass); + LoongarchIPIClass *lic = LOONGARCH_IPI_CLASS(klass); HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(klass); + device_class_set_parent_realize(dc, loongarch_ipi_realize, + &lic->parent_realize); licc->get_iocsr_as = get_iocsr_as; licc->cpu_by_arch_id = loongarch_cpu_by_arch_id; hc->plug = loongarch_cpu_plug; @@ -100,6 +123,7 @@ static const TypeInfo loongarch_ipi_types[] = { { .name = TYPE_LOONGARCH_IPI, .parent = TYPE_LOONGSON_IPI_COMMON, + .instance_size = sizeof(LoongarchIPIState), .class_init = loongarch_ipi_class_init, .interfaces = (InterfaceInfo[]) { { TYPE_HOTPLUG_HANDLER }, diff --git a/include/hw/intc/loongarch_ipi.h b/include/hw/intc/loongarch_ipi.h index 276b3040a3..1ef64af85c 100644 --- a/include/hw/intc/loongarch_ipi.h +++ b/include/hw/intc/loongarch_ipi.h @@ -10,16 +10,22 @@ #include "qom/object.h" #include "hw/intc/loongson_ipi_common.h" +#include "hw/loongarch/virt.h" +#define INVALID_CPU -1 #define TYPE_LOONGARCH_IPI "loongarch_ipi" OBJECT_DECLARE_TYPE(LoongarchIPIState, LoongarchIPIClass, LOONGARCH_IPI) struct LoongarchIPIState { LoongsonIPICommonState parent_obj; + DECLARE_BITMAP(present_cpu_map, LOONGARCH_MAX_CPUS); + int present_cpu[MAX_PHY_ID]; + CPUState *cs[MAX_PHY_ID]; }; struct LoongarchIPIClass { LoongsonIPICommonClass parent_class; + DeviceRealize parent_realize; }; #endif diff --git a/include/hw/loongarch/virt.h b/include/hw/loongarch/virt.h index 9ba47793ef..7754c85f0b 100644 --- a/include/hw/loongarch/virt.h +++ b/include/hw/loongarch/virt.h @@ -14,6 +14,15 @@ #include "hw/loongarch/boot.h" #define LOONGARCH_MAX_CPUS 256 +/* + * LoongArch Reference Manual Vol1, Chapter 7.4.12 CPU Identity + * For CPU architecture, bit0 .. bit8 is valid for CPU id, max cpuid is 512 + * However for IPI/Eiointc interrupt controller, max supported cpu id for + * irq routing is 256 + * + * Here max cpu id is 256 for virt machine + */ +#define MAX_PHY_ID 0x100 #define VIRT_FWCFG_BASE 0x1e020000UL #define VIRT_BIOS_BASE 0x1c000000UL -- 2.39.3
