Thanks Phil, I will send a v3 for follow-up. Regards, Sai Pavan
>-----Original Message----- >From: Philippe Mathieu-Daudé <phi...@linaro.org> >Sent: Thursday, October 31, 2024 9:30 PM >To: Simek, Michal <michal.si...@amd.com>; Alistair Francis ><alistai...@gmail.com>; Boddu, Sai Pavan <sai.pavan.bo...@amd.com> >Cc: qemu-devel@nongnu.org; qemu-ri...@nongnu.org; Paolo Bonzini ><pbonz...@redhat.com>; Palmer Dabbelt <pal...@dabbelt.com>; Alistair Francis ><alistair.fran...@wdc.com>; Bin Meng <bmeng...@gmail.com>; Weiwei Li ><liwei1...@gmail.com>; Daniel Henrique Barboza <dbarb...@ventanamicro.com>; >Liu Zhiwei <zhiwei_...@linux.alibaba.com> >Subject: Re: [PATCH v2] hw/riscv: Add Microblaze V 32bit virt board > >On 31/10/24 05:43, Michal Simek wrote: >> Hi, >> >> On 10/31/24 05:06, Philippe Mathieu-Daudé wrote: >>> Hi Michal, >>> >>> On 30/10/24 02:53, Michal Simek wrote: >>>> Hi Alistair, >>>> >>>> On 10/30/24 03:54, Alistair Francis wrote: >>>>> On Thu, Oct 17, 2024 at 5:26 PM Sai Pavan Boddu >>>>> <sai.pavan.bo...@amd.com> wrote: >>>> >>>>>> diff --git a/hw/riscv/microblaze-v-virt.c >>>>>> b/hw/riscv/microblaze-v-virt.c new file mode 100644 index >>>>>> 00000000000..6603e6d6b06 >>>>>> --- /dev/null >>>>>> +++ b/hw/riscv/microblaze-v-virt.c >>>>>> @@ -0,0 +1,181 @@ >>>>>> +/* >>>>>> + * QEMU model of Microblaze V (32bit version) >>> >>> Is there a 64-bit model planned? >> >> This guide is talking about 64bit too >> https://docs.amd.com/r/en-US/ug1629-microblaze-v-user-guide > >Same board, different core (synthesized with C_DATA_SIZE = 64). > >> It means answer is yes. And pretty much this generic model with the >> same layout should be possible to use with generic 64bit version too. >> >> I expect that means that default_cpu_type should be TYPE_RISCV_CPU_BASE. >> and Kconfig should be extended >> + depends on RISCV32 || RISCV64 >> >> Also some small updates in documentation to cover it. >> >> Is there something else what should be updated? > >No issue, I was just checking. > >Regards, > >Phil.
