Introduce support for the RISC-V vector extension in the TCG backend.
Changes for v7:
- Adjust cpuinfo-riscv.c probing for vector support.
In addition to adjusting @left, assert expected value in vlenb.
I wondered what would happen if a binary built for -march=rv64gv
was run on a host without vector support. In my case it got SIGILL
in another constructor before reaching cpuinfo_init(). But that's
certainly not guaranteed.
r~
Huang Shiyuan (1):
tcg/riscv: Add basic support for vector
Richard Henderson (3):
tcg: Reset data_gen_ptr correctly
disas/riscv: Fix vsetivli disassembly
tcg/riscv: Accept constant first argument to sub_vec
TANG Tiancheng (10):
util: Add RISC-V vector extension probe in cpuinfo
tcg/riscv: Implement vector mov/dup{m/i}
tcg/riscv: Add support for basic vector opcodes
tcg/riscv: Implement vector cmp/cmpsel ops
tcg/riscv: Implement vector neg ops
tcg/riscv: Implement vector sat/mul ops
tcg/riscv: Implement vector min/max ops
tcg/riscv: Implement vector shi/s/v ops
tcg/riscv: Implement vector roti/v/x ops
tcg/riscv: Enable native vector support for TCG host
disas/riscv.h | 2 +-
host/include/riscv/host/cpuinfo.h | 2 +
include/tcg/tcg.h | 6 +
tcg/riscv/tcg-target-con-set.h | 9 +
tcg/riscv/tcg-target-con-str.h | 3 +
tcg/riscv/tcg-target.h | 78 ++-
tcg/riscv/tcg-target.opc.h | 12 +
disas/riscv.c | 2 +-
tcg/tcg.c | 2 +-
util/cpuinfo-riscv.c | 34 +-
tcg/riscv/tcg-target.c.inc | 994 +++++++++++++++++++++++++++---
11 files changed, 1022 insertions(+), 122 deletions(-)
create mode 100644 tcg/riscv/tcg-target.opc.h
--
2.43.0
