On 10/14/24 6:04 AM, Frank Chang wrote:
Clément Léger <cle...@rivosinc.com> 於 2024年10月14日 週一 下午3:36寫道：
On 11/10/2024 13:38, Daniel Henrique Barboza wrote:
Hi Tommy,
Do you plan to send a new version of this work soon? This series is a
prerequisite
of "target/riscv: Add support for Smdbltrp and Ssdbltrp extensions" and
we need
this series merged first. We have minor comments from Clément and
Hi Henrique,
If that's easier, I can still remove the dependency on Smrnmi and add
support for that later.
Clément
Hi Clément,
Sorry for keeping you waiting. I've reviewed the comments from you and Alistair.
The comments should be straightforward to fix.
I will fix them and send out the patchset later today.
Hope that it makes things easier.
Thanks for taking care of this series Frank!
Daniel
Regards,
Frank Chang
Alistair so
hopefully it shouldn't be too much work.
The code freeze for 9.2 will happen in the first/second week of
November, so if you
could send a new version to be merged in the next PR that would be great.
Thanks,
Daniel
On 9/2/24 4:13 AM, Tommy Wu wrote:
This patchset added support for Smrnmi Extension in RISC-V.
There are four new CSRs and one new instruction added to allow NMI to be
resumable in RISC-V, which are:
=============================================================
* mnscratch (0x740)
* mnepc (0x741)
* mncause (0x742)
* mnstatus (0x744)
=============================================================
* mnret: To return from RNMI interrupt/exception handler.
=============================================================
RNMI also has higher priority than any other interrupts or exceptions
and cannot be disabled by software.
RNMI may be used to route to other devices such as Bus Error Unit or
Watchdog Timer in the future.
The interrupt/exception trap handler addresses of RNMI are
implementation defined.
If anyone wants to test the patches, we can use the customized
OpenSBI[1],
and the customized QEMU[2].
We implemented a PoC RNMI trap handler in the customized OpenSBI.
In the customized QEMU, we use the Smrnmi patches and the patch from
Damien Hedde[3]. The patch from Damien Hedde can be used to inject
the RNMI signal with the qmp command.
[1] https://github.com/TommyWu-fdgkhdkgh/opensbi/tree/dev/twu/master
[2] https://github.com/TommyWu-fdgkhdkgh/qemu/tree/dev/twu/master
[3] https://lists.gnu.org/archive/html/qemu-devel/2019-06/msg06232.html
Test commands :
$ ./build/qemu-system-riscv64 -M virt -cpu rv64,smrnmi=true,
rnmi-interrupt-vector={Offset of the RNMI handler in the customized
OpenSBI.} -m 4G -smp 2 -serial mon:stdio -serial null -nographic
-bios fw_jump.elf -kernel Image -initrd rootfs.cpio
-qmp unix:/tmp/qmp-sock,server,wait=off
Use qmp command to inject the RNMI interrupt.
$ ./scripts/qmp/qmp-shell /tmp/qmp-sock
(QEMU) gpio-set path=/machine/soc0/harts[0] gpio=riscv.cpu.rnmi
number=0 value=true
(QEMU) gpio-set path=/machine/soc0/harts[0] gpio=riscv.cpu.rnmi
number=0 value=false
Changelog:
v6
* Delete the redundant code in `riscv_cpu_do_interrupt`.
( Thank Alvin for the suggestion. )
* Split the shared code in `helper_mret` and `helper_mnret` into a
helper function `check_ret_from_m_mode`.
( Thank Alistair for the suggestion. )
v5
* Move the patch that adds the Smrnmi extension to the last patch.
( Thank Alistair for the suggestion. )
* Implement an M-mode software PoC for this with implemented handlers.
( Thank Andrew Jones for the suggestion. )
* Add a commit message to all patches of the series.
( Thank Andrew Jones for the suggestion. )
v4
* Fix some coding style issues.
( Thank Daniel for the suggestions. )
v3
* Update to the newest version of Smrnmi extension specification.
v2
* split up the series into more commits for convenience of review.
* add missing rnmi_irqvec and rnmi_excpvec properties to riscv_harts.
Tommy Wu (5):
target/riscv: Add `ext_smrnmi` in the RISCVCPUConfig.
target/riscv: Handle Smrnmi interrupt and exception.
target/riscv: Add Smrnmi CSRs.
target/riscv: Add Smrnmi mnret instruction.
target/riscv: Add Smrnmi cpu extension.
hw/riscv/riscv_hart.c | 18 ++++
include/hw/riscv/riscv_hart.h | 4 +
target/riscv/cpu.c | 18 ++++
target/riscv/cpu.h | 10 +++
target/riscv/cpu_bits.h | 23 ++++++
target/riscv/cpu_cfg.h | 1 +
target/riscv/cpu_helper.c | 80 ++++++++++++++++--
target/riscv/csr.c | 82 +++++++++++++++++++
target/riscv/helper.h | 1 +
target/riscv/insn32.decode | 3 +
.../riscv/insn_trans/trans_privileged.c.inc | 12 +++
target/riscv/op_helper.c | 49 +++++++++--
12 files changed, 291 insertions(+), 10 deletions(-)
