On Tue, 1 Oct 2024 at 10:51, Alexandra Diupina <[email protected]> wrote: > > The result of 1 << regbit with regbit==31 has a 1 in the 32nd bit. > When cast to uint64_t (for further bitwise OR), the 32 most > significant bits will be filled with 1s. However, the documentation > states that the upper 32 bits of ICH_AP[0/1]R<n>_EL2 are reserved. > > Add an explicit cast to match the documentation. > > Found by Linux Verification Center (linuxtesting.org) with SVACE. > > Fixes: d2c0c6aab6 ("hw/intc/arm_gicv3: Handle icv_nmiar1_read() for > icc_nmiar1_read()") > Signed-off-by: Alexandra Diupina <[email protected]>
Yep, these look definitely like fixes for wrong code. I've applied these to target-arm.next (with a cc to stable). PS: for future multi-patch submissions would you mind including a cover letter (of the form generated by 'git format-patch --cover-letter')? Our automated tools expect the cover letter, so patchsets are a bit easier to process if there is one. (Single patches don't need a cover letter.) thanks -- PMM
