On Thu, Jul 4, 2024 at 12:53 AM LIU Zhiwei <[email protected]> wrote: > > From: TANG Tiancheng <[email protected]> > > Ensure that riscv_cpu_sxl returns MXL_RV32 when runningRV32 in an > RV64 QEMU. > > Signed-off-by: TANG Tiancheng <[email protected]> > Fixes: 05e6ca5e156 ("target/riscv: Ignore reserved bits in PTE for RV64") > Reviewed-by: Liu Zhiwei <[email protected]>
Reviewed-by: Alistair Francis <[email protected]> Alistair > --- > target/riscv/cpu.h | 5 ++++- > 1 file changed, 4 insertions(+), 1 deletion(-) > > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index 87742047ce..49de81be7e 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -693,8 +693,11 @@ static inline RISCVMXL riscv_cpu_sxl(CPURISCVState *env) > #ifdef CONFIG_USER_ONLY > return env->misa_mxl; > #else > - return get_field(env->mstatus, MSTATUS64_SXL); > + if (env->misa_mxl != MXL_RV32) { > + return get_field(env->mstatus, MSTATUS64_SXL); > + } > #endif > + return MXL_RV32; > } > #endif > > -- > 2.25.1 > >
