The instructions have the same function as RVV1.0. Overall there are only general differences between XTheadVector and RVV1.0.
Signed-off-by: Huang Tao <[email protected]> --- target/riscv/helper.h | 33 +++++++ .../riscv/insn_trans/trans_xtheadvector.c.inc | 18 ++-- target/riscv/xtheadvector_helper.c | 87 +++++++++++++++++++ 3 files changed, 130 insertions(+), 8 deletions(-) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 93e6a3f33d..a6abb48b55 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1813,3 +1813,36 @@ DEF_HELPER_6(th_vwmulu_vx_w, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(th_vwmulsu_vx_b, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(th_vwmulsu_vx_h, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(th_vwmulsu_vx_w, void, ptr, ptr, tl, ptr, env, i32) + +DEF_HELPER_6(th_vmacc_vv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(th_vmacc_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(th_vmacc_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(th_vmacc_vv_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(th_vnmsac_vv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(th_vnmsac_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(th_vnmsac_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(th_vnmsac_vv_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(th_vmadd_vv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(th_vmadd_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(th_vmadd_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(th_vmadd_vv_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(th_vnmsub_vv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(th_vnmsub_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(th_vnmsub_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(th_vnmsub_vv_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(th_vmacc_vx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(th_vmacc_vx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(th_vmacc_vx_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(th_vmacc_vx_d, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(th_vnmsac_vx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(th_vnmsac_vx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(th_vnmsac_vx_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(th_vnmsac_vx_d, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(th_vmadd_vx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(th_vmadd_vx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(th_vmadd_vx_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(th_vmadd_vx_d, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(th_vnmsub_vx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(th_vnmsub_vx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(th_vnmsub_vx_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(th_vnmsub_vx_d, void, ptr, ptr, tl, ptr, env, i32) diff --git a/target/riscv/insn_trans/trans_xtheadvector.c.inc b/target/riscv/insn_trans/trans_xtheadvector.c.inc index 681e967078..d84edd90ca 100644 --- a/target/riscv/insn_trans/trans_xtheadvector.c.inc +++ b/target/riscv/insn_trans/trans_xtheadvector.c.inc @@ -1557,20 +1557,22 @@ GEN_OPIVX_WIDEN_TRANS_TH(th_vwmul_vx, opivx_widen_check_th) GEN_OPIVX_WIDEN_TRANS_TH(th_vwmulu_vx, opivx_widen_check_th) GEN_OPIVX_WIDEN_TRANS_TH(th_vwmulsu_vx, opivx_widen_check_th) +/* Vector Single-Width Integer Multiply-Add Instructions */ +GEN_OPIVV_TRANS_TH(th_vmacc_vv, opivv_check_th) +GEN_OPIVV_TRANS_TH(th_vnmsac_vv, opivv_check_th) +GEN_OPIVV_TRANS_TH(th_vmadd_vv, opivv_check_th) +GEN_OPIVV_TRANS_TH(th_vnmsub_vv, opivv_check_th) +GEN_OPIVX_TRANS_TH(th_vmacc_vx, opivx_check_th) +GEN_OPIVX_TRANS_TH(th_vnmsac_vx, opivx_check_th) +GEN_OPIVX_TRANS_TH(th_vmadd_vx, opivx_check_th) +GEN_OPIVX_TRANS_TH(th_vnmsub_vx, opivx_check_th) + #define TH_TRANS_STUB(NAME) \ static bool trans_##NAME(DisasContext *s, arg_##NAME *a) \ { \ return require_xtheadvector(s); \ } -TH_TRANS_STUB(th_vmacc_vv) -TH_TRANS_STUB(th_vmacc_vx) -TH_TRANS_STUB(th_vnmsac_vv) -TH_TRANS_STUB(th_vnmsac_vx) -TH_TRANS_STUB(th_vmadd_vv) -TH_TRANS_STUB(th_vmadd_vx) -TH_TRANS_STUB(th_vnmsub_vv) -TH_TRANS_STUB(th_vnmsub_vx) TH_TRANS_STUB(th_vwmaccu_vv) TH_TRANS_STUB(th_vwmaccu_vx) TH_TRANS_STUB(th_vwmacc_vv) diff --git a/target/riscv/xtheadvector_helper.c b/target/riscv/xtheadvector_helper.c index b5b1e55452..ccf6eb8a43 100644 --- a/target/riscv/xtheadvector_helper.c +++ b/target/riscv/xtheadvector_helper.c @@ -1791,3 +1791,90 @@ GEN_TH_VX(th_vwmulu_vx_w, 4, 8, clearq_th) GEN_TH_VX(th_vwmulsu_vx_b, 1, 2, clearh_th) GEN_TH_VX(th_vwmulsu_vx_h, 2, 4, clearl_th) GEN_TH_VX(th_vwmulsu_vx_w, 4, 8, clearq_th) + +/* Vector Single-Width Integer Multiply-Add Instructions */ +#define TH_OPIVV3(NAME, TD, T1, T2, TX1, TX2, HD, HS1, HS2, OP) \ +static void do_##NAME(void *vd, void *vs1, void *vs2, int i) \ +{ \ + TX1 s1 = *((T1 *)vs1 + HS1(i)); \ + TX2 s2 = *((T2 *)vs2 + HS2(i)); \ + TD d = *((TD *)vd + HD(i)); \ + *((TD *)vd + HD(i)) = OP(s2, s1, d); \ +} +#define TH_MACC(N, M, D) (M * N + D) +#define TH_NMSAC(N, M, D) (-(M * N) + D) +#define TH_MADD(N, M, D) (M * D + N) +#define TH_NMSUB(N, M, D) (-(M * D) + N) +THCALL(TH_OPIVV3, th_vmacc_vv_b, OP_SSS_B, H1, H1, H1, TH_MACC) +THCALL(TH_OPIVV3, th_vmacc_vv_h, OP_SSS_H, H2, H2, H2, TH_MACC) +THCALL(TH_OPIVV3, th_vmacc_vv_w, OP_SSS_W, H4, H4, H4, TH_MACC) +THCALL(TH_OPIVV3, th_vmacc_vv_d, OP_SSS_D, H8, H8, H8, TH_MACC) +THCALL(TH_OPIVV3, th_vnmsac_vv_b, OP_SSS_B, H1, H1, H1, TH_NMSAC) +THCALL(TH_OPIVV3, th_vnmsac_vv_h, OP_SSS_H, H2, H2, H2, TH_NMSAC) +THCALL(TH_OPIVV3, th_vnmsac_vv_w, OP_SSS_W, H4, H4, H4, TH_NMSAC) +THCALL(TH_OPIVV3, th_vnmsac_vv_d, OP_SSS_D, H8, H8, H8, TH_NMSAC) +THCALL(TH_OPIVV3, th_vmadd_vv_b, OP_SSS_B, H1, H1, H1, TH_MADD) +THCALL(TH_OPIVV3, th_vmadd_vv_h, OP_SSS_H, H2, H2, H2, TH_MADD) +THCALL(TH_OPIVV3, th_vmadd_vv_w, OP_SSS_W, H4, H4, H4, TH_MADD) +THCALL(TH_OPIVV3, th_vmadd_vv_d, OP_SSS_D, H8, H8, H8, TH_MADD) +THCALL(TH_OPIVV3, th_vnmsub_vv_b, OP_SSS_B, H1, H1, H1, TH_NMSUB) +THCALL(TH_OPIVV3, th_vnmsub_vv_h, OP_SSS_H, H2, H2, H2, TH_NMSUB) +THCALL(TH_OPIVV3, th_vnmsub_vv_w, OP_SSS_W, H4, H4, H4, TH_NMSUB) +THCALL(TH_OPIVV3, th_vnmsub_vv_d, OP_SSS_D, H8, H8, H8, TH_NMSUB) +GEN_TH_VV(th_vmacc_vv_b, 1, 1, clearb_th) +GEN_TH_VV(th_vmacc_vv_h, 2, 2, clearh_th) +GEN_TH_VV(th_vmacc_vv_w, 4, 4, clearl_th) +GEN_TH_VV(th_vmacc_vv_d, 8, 8, clearq_th) +GEN_TH_VV(th_vnmsac_vv_b, 1, 1, clearb_th) +GEN_TH_VV(th_vnmsac_vv_h, 2, 2, clearh_th) +GEN_TH_VV(th_vnmsac_vv_w, 4, 4, clearl_th) +GEN_TH_VV(th_vnmsac_vv_d, 8, 8, clearq_th) +GEN_TH_VV(th_vmadd_vv_b, 1, 1, clearb_th) +GEN_TH_VV(th_vmadd_vv_h, 2, 2, clearh_th) +GEN_TH_VV(th_vmadd_vv_w, 4, 4, clearl_th) +GEN_TH_VV(th_vmadd_vv_d, 8, 8, clearq_th) +GEN_TH_VV(th_vnmsub_vv_b, 1, 1, clearb_th) +GEN_TH_VV(th_vnmsub_vv_h, 2, 2, clearh_th) +GEN_TH_VV(th_vnmsub_vv_w, 4, 4, clearl_th) +GEN_TH_VV(th_vnmsub_vv_d, 8, 8, clearq_th) + +#define TH_OPIVX3(NAME, TD, T1, T2, TX1, TX2, HD, HS2, OP) \ +static void do_##NAME(void *vd, target_long s1, void *vs2, int i) \ +{ \ + TX2 s2 = *((T2 *)vs2 + HS2(i)); \ + TD d = *((TD *)vd + HD(i)); \ + *((TD *)vd + HD(i)) = OP(s2, (TX1)(T1)s1, d); \ +} + +THCALL(TH_OPIVX3, th_vmacc_vx_b, OP_SSS_B, H1, H1, TH_MACC) +THCALL(TH_OPIVX3, th_vmacc_vx_h, OP_SSS_H, H2, H2, TH_MACC) +THCALL(TH_OPIVX3, th_vmacc_vx_w, OP_SSS_W, H4, H4, TH_MACC) +THCALL(TH_OPIVX3, th_vmacc_vx_d, OP_SSS_D, H8, H8, TH_MACC) +THCALL(TH_OPIVX3, th_vnmsac_vx_b, OP_SSS_B, H1, H1, TH_NMSAC) +THCALL(TH_OPIVX3, th_vnmsac_vx_h, OP_SSS_H, H2, H2, TH_NMSAC) +THCALL(TH_OPIVX3, th_vnmsac_vx_w, OP_SSS_W, H4, H4, TH_NMSAC) +THCALL(TH_OPIVX3, th_vnmsac_vx_d, OP_SSS_D, H8, H8, TH_NMSAC) +THCALL(TH_OPIVX3, th_vmadd_vx_b, OP_SSS_B, H1, H1, TH_MADD) +THCALL(TH_OPIVX3, th_vmadd_vx_h, OP_SSS_H, H2, H2, TH_MADD) +THCALL(TH_OPIVX3, th_vmadd_vx_w, OP_SSS_W, H4, H4, TH_MADD) +THCALL(TH_OPIVX3, th_vmadd_vx_d, OP_SSS_D, H8, H8, TH_MADD) +THCALL(TH_OPIVX3, th_vnmsub_vx_b, OP_SSS_B, H1, H1, TH_NMSUB) +THCALL(TH_OPIVX3, th_vnmsub_vx_h, OP_SSS_H, H2, H2, TH_NMSUB) +THCALL(TH_OPIVX3, th_vnmsub_vx_w, OP_SSS_W, H4, H4, TH_NMSUB) +THCALL(TH_OPIVX3, th_vnmsub_vx_d, OP_SSS_D, H8, H8, TH_NMSUB) +GEN_TH_VX(th_vmacc_vx_b, 1, 1, clearb_th) +GEN_TH_VX(th_vmacc_vx_h, 2, 2, clearh_th) +GEN_TH_VX(th_vmacc_vx_w, 4, 4, clearl_th) +GEN_TH_VX(th_vmacc_vx_d, 8, 8, clearq_th) +GEN_TH_VX(th_vnmsac_vx_b, 1, 1, clearb_th) +GEN_TH_VX(th_vnmsac_vx_h, 2, 2, clearh_th) +GEN_TH_VX(th_vnmsac_vx_w, 4, 4, clearl_th) +GEN_TH_VX(th_vnmsac_vx_d, 8, 8, clearq_th) +GEN_TH_VX(th_vmadd_vx_b, 1, 1, clearb_th) +GEN_TH_VX(th_vmadd_vx_h, 2, 2, clearh_th) +GEN_TH_VX(th_vmadd_vx_w, 4, 4, clearl_th) +GEN_TH_VX(th_vmadd_vx_d, 8, 8, clearq_th) +GEN_TH_VX(th_vnmsub_vx_b, 1, 1, clearb_th) +GEN_TH_VX(th_vnmsub_vx_h, 2, 2, clearh_th) +GEN_TH_VX(th_vnmsub_vx_w, 4, 4, clearl_th) +GEN_TH_VX(th_vnmsub_vx_d, 8, 8, clearq_th) -- 2.44.0
