-- Empty commit to align the patch numbers between PATCH v1 and PATCH v2. SPI responder model is removed as pnv spi controller and seeprom is implemented using QEMU SSI framework.
Signed-off-by: Chalapathi V <[email protected]>
- [PATCH v2 0/6] hw/ppc: SPI model Chalapathi V
- [PATCH v2 3/6] hw/ppc: SPI controller model - seque... Chalapathi V
- Re: [PATCH v2 3/6] hw/ppc: SPI controller model... Cédric Le Goater
- Re: [PATCH v2 3/6] hw/ppc: SPI controller m... Chalapathi V
- [PATCH v2 1/6] hw/ppc: remove SPI responder model Chalapathi V
- Re: [PATCH v2 1/6] hw/ppc: remove SPI responder... Cédric Le Goater
- [PATCH v2 2/6] hw/ppc: SPI controller model - regis... Chalapathi V
- Re: [PATCH v2 2/6] hw/ppc: SPI controller model... Cédric Le Goater
- Re: [PATCH v2 2/6] hw/ppc: SPI controller m... Chalapathi V
- Re: [PATCH v2 2/6] hw/ppc: SPI controll... Cédric Le Goater
- [PATCH v2 4/6] hw/misc: Microchip's 25CSM04 SEEPROM... Chalapathi V
- Re: [PATCH v2 4/6] hw/misc: Microchip's 25CSM04... Cédric Le Goater
- [PATCH v2 6/6] tests/qtest: Add pnv-spi-seeprom qte... Chalapathi V
- [PATCH v2 5/6] hw/ppc: SPI controller wiring to P10... Chalapathi V
- Re: [PATCH v2 5/6] hw/ppc: SPI controller wirin... Cédric Le Goater
