Using the correct space for BE,L linkage might make the difference
for a cpu stress test. I believe triggering this would require
something like
f=(seg,ofs), b=(seg,ofs+4)
be 0(sr1,r1) f=(seg,ofs+4), b=(sr1,r1)
be,l,n 0(sr2,r2),sr0,r31 f=(sr1,r1), b=(sr2,r2)
and then validating the contents of sr0 on return.
Linux only places B,GATE in the zero page, so amusingly there were
never any high bits to clobber. But I can imagine HP-UX making
more use of gateway pages, and certainly a cpu stress test would.
r~
Richard Henderson (2):
target/hppa: Fix BE,L set of sr0
target/hppa: Fix B,GATE for wide mode
target/hppa/translate.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
--
2.34.1
