On Tue Mar 12, 2024 at 8:03 PM AEST, Harsh Prateek Bora wrote:
>
>
> On 3/12/24 00:21, Nicholas Piggin wrote:
> > The initial MSR state for PAPR specifies MSR[ME] and MSR[FP] are set.
> > 
> > Signed-off-by: Nicholas Piggin <[email protected]>
>
> It would be good to mention PAPR section numbers suggesting the same.

I'll see if I can find it and put it in a comment.

Thanks,
Nick

> Anyways,
>
> Reviewed-by: Harsh Prateek Bora <[email protected]>
>
> > ---
> >   hw/ppc/spapr_cpu_core.c | 2 ++
> >   1 file changed, 2 insertions(+)
> > 
> > diff --git a/hw/ppc/spapr_cpu_core.c b/hw/ppc/spapr_cpu_core.c
> > index 50523ead25..f3b01b0801 100644
> > --- a/hw/ppc/spapr_cpu_core.c
> > +++ b/hw/ppc/spapr_cpu_core.c
> > @@ -42,6 +42,8 @@ static void spapr_reset_vcpu(PowerPCCPU *cpu)
> >        * as 32bit (MSR_SF=0) in "8.2.1. Initial Register Values".
> >        */
> >       env->msr &= ~(1ULL << MSR_SF);
> > +    env->msr |= (1ULL << MSR_ME) | (1ULL << MSR_FP);
> > +
> >       env->spr[SPR_HIOR] = 0;
> >   
> >       lpcr = env->spr[SPR_LPCR];


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