Add support for Zve64x extension. Enabling Zve64f enables Zve64x and enabling Zve64x enables Zve32x according to their dependency.
Signed-off-by: Jason Chien <[email protected]> Reviewed-by: Frank Chang <[email protected]> Reviewed-by: Max Chou <[email protected]> --- target/riscv/cpu.c | 1 + target/riscv/cpu_cfg.h | 1 + target/riscv/tcg/tcg-cpu.c | 17 +++++++++++------ 3 files changed, 13 insertions(+), 6 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 37e4557b47..8b5d1eb6a8 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -155,6 +155,7 @@ const RISCVIsaExtData isa_edata_arr[] = { ISA_EXT_DATA_ENTRY(zve32x, PRIV_VERSION_1_10_0, ext_zve32x), ISA_EXT_DATA_ENTRY(zve64f, PRIV_VERSION_1_10_0, ext_zve64f), ISA_EXT_DATA_ENTRY(zve64d, PRIV_VERSION_1_10_0, ext_zve64d), + ISA_EXT_DATA_ENTRY(zve64x, PRIV_VERSION_1_10_0, ext_zve64x), ISA_EXT_DATA_ENTRY(zvfbfmin, PRIV_VERSION_1_12_0, ext_zvfbfmin), ISA_EXT_DATA_ENTRY(zvfbfwma, PRIV_VERSION_1_12_0, ext_zvfbfwma), ISA_EXT_DATA_ENTRY(zvfh, PRIV_VERSION_1_12_0, ext_zvfh), diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index beb3d10213..5d99856822 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -93,6 +93,7 @@ struct RISCVCPUConfig { bool ext_zve32x; bool ext_zve64f; bool ext_zve64d; + bool ext_zve64x; bool ext_zvbb; bool ext_zvbc; bool ext_zvkb; diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index ce539528e6..d630879286 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -488,17 +488,22 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) /* The Zve64d extension depends on the Zve64f extension */ if (cpu->cfg.ext_zve64d) { + if (!riscv_has_ext(env, RVD)) { + error_setg(errp, "Zve64d/V extensions require D extension"); + return; + } cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve64f), true); } - /* The Zve64f extension depends on the Zve32f extension */ + /* The Zve64f extension depends on the Zve64x and Zve32f extensions */ if (cpu->cfg.ext_zve64f) { + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve64x), true); cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve32f), true); } - if (cpu->cfg.ext_zve64d && !riscv_has_ext(env, RVD)) { - error_setg(errp, "Zve64d/V extensions require D extension"); - return; + /* The Zve64x extension depends on the Zve32x extension */ + if (cpu->cfg.ext_zve64x) { + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve32x), true); } /* The Zve32f extension depends on the Zve32x extension */ @@ -665,10 +670,10 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) return; } - if ((cpu->cfg.ext_zvbc || cpu->cfg.ext_zvknhb) && !cpu->cfg.ext_zve64f) { + if ((cpu->cfg.ext_zvbc || cpu->cfg.ext_zvknhb) && !cpu->cfg.ext_zve64x) { error_setg( errp, - "Zvbc and Zvknhb extensions require V or Zve64{f,d} extensions"); + "Zvbc and Zvknhb extensions require V or Zve64x extensions"); return; } -- 2.43.2
