On 03/13/2012 07:14 PM, Peter Maydell wrote:
>> This change seems to drop the MCRR block cache op handling and I don't
>> see anything elsewhere which implements it. This will presumably break
>> some CPU/guest combination.
>
> Do you have any pointer on that exactly did we try to emulate here?
No. You'll need to check the TRMs for every CPU core we claim to
emulate and the ARM ARM (including the ARMv6 and ARMv5 versions
as well as the current revision). Yes, this is a really painful
chore. You'll also need to try to round up some images so you can
test at least a handful of them.
(I've been ploughing through this for the 32 bit registers as part
of trying to convert them to a more data driven implementation.)
There is B3.15.1 block in the ARM ARM, it says that there were no 64-bit access
to system registers before LPAE and Generic Timer. Do you mean that some 64-bit
system registers were defined for specific CPUs?
Thanks,
Alex.
