On 9/2/24 09:53, Philippe Mathieu-Daudé wrote:
Desperate attempt to enable access from ITU to SAAR registers, by taking missing part of commits c9340491cc ("target-mips: implement SAARI/SAAR registers") and c1af807054 ("target-mips: add I6500 core configuration") from [*] which were partly committed as 5fb2dcd179 ("target/mips: Provide R/W access to SAARI and SAAR CP0 registers").[*] https://github.com/MIPS/qemu/commit/c9340491cc. Reported-by: Paolo Bonzini <[email protected]> Signed-off-by: Philippe Mathieu-Daudé <[email protected]> --- I can not test this. We don't test the I6500 anyway. Besides this CPU lacks DSPRAM support which was never merged, see: https://lore.kernel.org/qemu-devel/[email protected]/ and: https://github.com/MIPS/qemu/commit/a4c1477c84#diff-5362bb61a4a73490270458b19e452bac9b3b907f4efd59ece6494ec19d033a81 so I doubt it is really useful in its current incomplete state. --- target/mips/cpu.c | 1 + target/mips/tcg/translate.c | 1 + target/mips/cpu-defs.c.inc | 1 + 3 files changed, 3 insertions(+)
Patch discarded in favor of: https://lore.kernel.org/qemu-devel/[email protected]/
