On Thu, 2023-10-19 at 01:00 +0100, David Woodhouse wrote: > From: David Woodhouse <[email protected]> > > The interrupt from timer 0 in legacy mode is supposed to go to IRQ 0 on > the i8259 and IRQ 2 on the I/O APIC. The generic x86 GSI handling can't > cope with IRQ numbers differing between the two chips (despite it also > being the case for PCI INTx routing), so add a special case for the HPET. > > IRQ 2 isn't valid on the i8259; it's the cascade IRQ and would be > interpreted as spurious interrupt on the secondary PIC. So we can fix > up all attempts to deliver IRQ2, to actually deliver to IRQ0 on the PIC. > > Signed-off-by: David Woodhouse <[email protected]>
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