Il lun 8 gen 2024, 22:45 Richard Henderson <[email protected]> ha scritto:
> > I was thinking: a lot of RISC targets simply do AND/ANDI > > followed by the sequence used for TCG_COND_NE. Would it make sense to > > have a TCG_TARGET_SUPPORTS_TST bit and, if absent, lower TSTEQ/TSTNE > > to AND+EQ/NE directly in the optimizer? > > Probably best, yes. > Ok, I will give it a shot. > And for brcond2/setcond2, > > always using AND/AND/OR may work just as well as any backend-specific > > trick, and will give more freedom to the register allocator. > > test a,b > testeq c,e > > for Arm32. So I'll leave it to the backends. > Nice. :) Paolo > > r~ > >
