On Tue, 7 Nov 2023 at 02:36, Alistair Francis <[email protected]> wrote: > > From: Rob Bradford <[email protected]> > > Check the PMU available bitmask when checking if a counter is valid > rather than comparing the index against the number of PMUs. > > Signed-off-by: Rob Bradford <[email protected]> > Reviewed-by: LIU Zhiwei <[email protected]> > Reviewed-by: Alistair Francis <[email protected]> > Reviewed-by: Atish Patra <[email protected]> > Message-ID: <[email protected]> > Signed-off-by: Alistair Francis <[email protected]> > --- > target/riscv/csr.c | 5 +++-- > 1 file changed, 3 insertions(+), 2 deletions(-) > > diff --git a/target/riscv/csr.c b/target/riscv/csr.c > index fc26b52c88..fde7ce1a53 100644 > --- a/target/riscv/csr.c > +++ b/target/riscv/csr.c > @@ -188,7 +188,8 @@ static RISCVException zcmt(CPURISCVState *env, int csrno) > #if !defined(CONFIG_USER_ONLY) > static RISCVException mctr(CPURISCVState *env, int csrno) > { > - int pmu_num = riscv_cpu_cfg(env)->pmu_num; > + RISCVCPU *cpu = env_archcpu(env); > + uint32_t pmu_avail_ctrs = cpu->pmu_avail_ctrs; > int ctr_index; > int base_csrno = CSR_MHPMCOUNTER3; > > @@ -197,7 +198,7 @@ static RISCVException mctr(CPURISCVState *env, int csrno) > base_csrno += 0x80; > } > ctr_index = csrno - base_csrno; > - if (!pmu_num || ctr_index >= pmu_num) { > + if ((BIT(ctr_index) & pmu_avail_ctrs >> 3) == 0) { > /* The PMU is not enabled or counter is out of range */ > return RISCV_EXCP_ILLEGAL_INST; > }
Hi; Coverity is not convinced that ctr_index is necessarily guaranteed to be within the valid range to be an argument to BIT() (eg that it won't be negative). Looking at the code as a human I'm pretty unsure too. Could somebody have a look at this and maybe improve the readability / add an assertion / fix a bug if any ? (CID 1523910) More generally there are about half a dozen other riscv issues in Coverity at the moment, so if somebody who knows the riscv code could have a look at them that would be great. thanks -- PMM
