On Fri, Oct 27, 2023 at 1:21 AM Max Chou <[email protected]> wrote: > > The Zvkb extension is a proper subset of the Zvbb extension and includes > following instructions: > * vandn.[vv,vx] > * vbrev8.v > * vrev8.v > * vrol.[vv,vx] > * vror.[vv,vx,vi] > > Signed-off-by: Max Chou <[email protected]>
Acked-by: Alistair Francis <[email protected]> Alistair > --- > target/riscv/insn_trans/trans_rvvk.c.inc | 37 +++++++++++++++--------- > 1 file changed, 24 insertions(+), 13 deletions(-) > > diff --git a/target/riscv/insn_trans/trans_rvvk.c.inc > b/target/riscv/insn_trans/trans_rvvk.c.inc > index e691519ed78..3801c16829d 100644 > --- a/target/riscv/insn_trans/trans_rvvk.c.inc > +++ b/target/riscv/insn_trans/trans_rvvk.c.inc > @@ -112,24 +112,27 @@ GEN_VX_MASKED_TRANS(vclmulh_vx, vclmul_vx_check) > return false; \ > } > > -static bool zvbb_vv_check(DisasContext *s, arg_rmrr *a) > +static bool zvkb_vv_check(DisasContext *s, arg_rmrr *a) > { > - return opivv_check(s, a) && s->cfg_ptr->ext_zvbb == true; > + return opivv_check(s, a) && > + (s->cfg_ptr->ext_zvbb == true || s->cfg_ptr->ext_zvkb == true); > } > > -static bool zvbb_vx_check(DisasContext *s, arg_rmrr *a) > +static bool zvkb_vx_check(DisasContext *s, arg_rmrr *a) > { > - return opivx_check(s, a) && s->cfg_ptr->ext_zvbb == true; > + return opivx_check(s, a) && > + (s->cfg_ptr->ext_zvbb == true || s->cfg_ptr->ext_zvkb == true); > } > > /* vrol.v[vx] */ > -GEN_OPIVV_GVEC_TRANS_CHECK(vrol_vv, rotlv, zvbb_vv_check) > -GEN_OPIVX_GVEC_SHIFT_TRANS_CHECK(vrol_vx, rotls, zvbb_vx_check) > +GEN_OPIVV_GVEC_TRANS_CHECK(vrol_vv, rotlv, zvkb_vv_check) > +GEN_OPIVX_GVEC_SHIFT_TRANS_CHECK(vrol_vx, rotls, zvkb_vx_check) > > /* vror.v[vxi] */ > -GEN_OPIVV_GVEC_TRANS_CHECK(vror_vv, rotrv, zvbb_vv_check) > -GEN_OPIVX_GVEC_SHIFT_TRANS_CHECK(vror_vx, rotrs, zvbb_vx_check) > -GEN_OPIVI_GVEC_TRANS_CHECK(vror_vi, IMM_TRUNC_SEW, vror_vx, rotri, > zvbb_vx_check) > +GEN_OPIVV_GVEC_TRANS_CHECK(vror_vv, rotrv, zvkb_vv_check) > +GEN_OPIVX_GVEC_SHIFT_TRANS_CHECK(vror_vx, rotrs, zvkb_vx_check) > +GEN_OPIVI_GVEC_TRANS_CHECK(vror_vi, IMM_TRUNC_SEW, vror_vx, rotri, > + zvkb_vx_check) > > #define GEN_OPIVX_GVEC_TRANS_CHECK(NAME, SUF, CHECK) \ > static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ > @@ -147,8 +150,8 @@ GEN_OPIVI_GVEC_TRANS_CHECK(vror_vi, IMM_TRUNC_SEW, > vror_vx, rotri, zvbb_vx_check > } > > /* vandn.v[vx] */ > -GEN_OPIVV_GVEC_TRANS_CHECK(vandn_vv, andc, zvbb_vv_check) > -GEN_OPIVX_GVEC_TRANS_CHECK(vandn_vx, andcs, zvbb_vx_check) > +GEN_OPIVV_GVEC_TRANS_CHECK(vandn_vv, andc, zvkb_vv_check) > +GEN_OPIVX_GVEC_TRANS_CHECK(vandn_vx, andcs, zvkb_vx_check) > > #define GEN_OPIV_TRANS(NAME, CHECK) \ > static bool trans_##NAME(DisasContext *s, arg_rmr *a) \ > @@ -188,8 +191,16 @@ static bool zvbb_opiv_check(DisasContext *s, arg_rmr *a) > vext_check_ss(s, a->rd, a->rs2, a->vm); > } > > -GEN_OPIV_TRANS(vbrev8_v, zvbb_opiv_check) > -GEN_OPIV_TRANS(vrev8_v, zvbb_opiv_check) > +static bool zvkb_opiv_check(DisasContext *s, arg_rmr *a) > +{ > + return (s->cfg_ptr->ext_zvbb == true || s->cfg_ptr->ext_zvkb == true) && > + require_rvv(s) && > + vext_check_isa_ill(s) && > + vext_check_ss(s, a->rd, a->rs2, a->vm); > +} > + > +GEN_OPIV_TRANS(vbrev8_v, zvkb_opiv_check) > +GEN_OPIV_TRANS(vrev8_v, zvkb_opiv_check) > GEN_OPIV_TRANS(vbrev_v, zvbb_opiv_check) > GEN_OPIV_TRANS(vclz_v, zvbb_opiv_check) > GEN_OPIV_TRANS(vctz_v, zvbb_opiv_check) > -- > 2.34.1 > >
