> -----Original Message----- > From: Philippe Mathieu-Daudé <[email protected]> > Sent: Friday, October 13, 2023 9:01 AM > To: [email protected] > Cc: Eduardo Habkost <[email protected]>; Xiaojuan Yang > <[email protected]>; Michael S. Tsirkin <[email protected]>; qemu- > [email protected]; Aleksandar Rikalo <[email protected]>; David > Hildenbrand <[email protected]>; [email protected]; Edgar E. Iglesias > <[email protected]>; Jiaxun Yang <[email protected]>; Song > Gao <[email protected]>; Philippe Mathieu-Daudé <[email protected]>; > Paolo Bonzini <[email protected]>; Stafford Horne <[email protected]>; > Alistair Francis <[email protected]>; Yanan Wang > <[email protected]>; Max Filippov <[email protected]>; Artyom > Tarasenko <[email protected]>; Marcel Apfelbaum > <[email protected]>; Cédric Le Goater <[email protected]>; Laurent > Vivier <[email protected]>; Aurelien Jarno <[email protected]>; qemu- > [email protected]; Palmer Dabbelt <[email protected]>; Yoshinori Sato > <[email protected]>; Bastian Koppelmann <[email protected] > paderborn.de>; Bin Meng <[email protected]>; Daniel Henrique > Barboza <[email protected]>; Mark Cave-Ayland <mark.cave- > [email protected]>; Weiwei Li <[email protected]>; Daniel Henrique > Barboza <[email protected]>; Nicholas Piggin > <[email protected]>; [email protected]; Liu Zhiwei > <[email protected]>; Marek Vasut <[email protected]>; Laurent > Vivier <[email protected]>; Peter Maydell <[email protected]>; Brian > Cain <[email protected]>; Thomas Huth <[email protected]>; Chris Wulff > <[email protected]>; Sergio Lopez <[email protected]>; Richard Henderson > <[email protected]>; Ilya Leoshkevich <[email protected]>; > Michael Rolnik <[email protected]> > Subject: [PATCH v2 07/16] target/hexagon: Declare QOM definitions in 'cpu- > qom.h' > > WARNING: This email originated from outside of Qualcomm. Please be wary of > any links or attachments, and do not enable macros. > > "target/foo/cpu.h" contains the target specific declarations. > > A heterogeneous setup need to access target agnostic declarations > (at least the QOM ones, to instantiate the objects). > > Our convention is to add such target agnostic QOM declarations in > the "target/foo/cpu-qom.h" header. > > Extract QOM definitions from "cpu.h" to "cpu-qom.h". > > Signed-off-by: Philippe Mathieu-Daudé <[email protected]> > --- > target/hexagon/cpu-qom.h | 28 ++++++++++++++++++++++++++++ > target/hexagon/cpu.h | 15 +-------------- > 2 files changed, 29 insertions(+), 14 deletions(-) > create mode 100644 target/hexagon/cpu-qom.h > > diff --git a/target/hexagon/cpu-qom.h b/target/hexagon/cpu-qom.h > new file mode 100644 > index 0000000000..f02df7ee6f > --- /dev/null > +++ b/target/hexagon/cpu-qom.h > @@ -0,0 +1,28 @@ > +/* > + * QEMU Hexagon CPU QOM header (target agnostic) > + * > + * Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights > Reserved. > + * > + * SPDX-License-Identifier: GPL-2.0-or-later > + */ > + > +#ifndef QEMU_HEXAGON_CPU_QOM_H > +#define QEMU_HEXAGON_CPU_QOM_H > + > +#include "hw/core/cpu.h" > +#include "qom/object.h" > + > +#define TYPE_HEXAGON_CPU "hexagon-cpu" > + > +#define HEXAGON_CPU_TYPE_SUFFIX "-" TYPE_HEXAGON_CPU > +#define HEXAGON_CPU_TYPE_NAME(name) (name > HEXAGON_CPU_TYPE_SUFFIX) > + > +#define TYPE_HEXAGON_CPU_V67 HEXAGON_CPU_TYPE_NAME("v67") > +#define TYPE_HEXAGON_CPU_V68 HEXAGON_CPU_TYPE_NAME("v68") > +#define TYPE_HEXAGON_CPU_V69 HEXAGON_CPU_TYPE_NAME("v69") > +#define TYPE_HEXAGON_CPU_V71 HEXAGON_CPU_TYPE_NAME("v71") > +#define TYPE_HEXAGON_CPU_V73 HEXAGON_CPU_TYPE_NAME("v73") > + > +OBJECT_DECLARE_CPU_TYPE(HexagonCPU, HexagonCPUClass, > HEXAGON_CPU) > + > +#endif > diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h > index 035ac4fb6d..7d16083c6a 100644 > --- a/target/hexagon/cpu.h > +++ b/target/hexagon/cpu.h > @@ -20,11 +20,10 @@ > > #include "fpu/softfloat-types.h" > > +#include "cpu-qom.h" > #include "exec/cpu-defs.h" > #include "hex_regs.h" > #include "mmvec/mmvec.h" > -#include "qom/object.h" > -#include "hw/core/cpu.h" > #include "hw/registerfields.h" > > #define NUM_PREGS 4 > @@ -36,18 +35,8 @@ > #define PRED_WRITES_MAX 5 /* 4 insns + endloop */ > #define VSTORES_MAX 2 > > -#define TYPE_HEXAGON_CPU "hexagon-cpu" > - > -#define HEXAGON_CPU_TYPE_SUFFIX "-" TYPE_HEXAGON_CPU > -#define HEXAGON_CPU_TYPE_NAME(name) (name > HEXAGON_CPU_TYPE_SUFFIX) > #define CPU_RESOLVING_TYPE TYPE_HEXAGON_CPU > > -#define TYPE_HEXAGON_CPU_V67 HEXAGON_CPU_TYPE_NAME("v67") > -#define TYPE_HEXAGON_CPU_V68 HEXAGON_CPU_TYPE_NAME("v68") > -#define TYPE_HEXAGON_CPU_V69 HEXAGON_CPU_TYPE_NAME("v69") > -#define TYPE_HEXAGON_CPU_V71 HEXAGON_CPU_TYPE_NAME("v71") > -#define TYPE_HEXAGON_CPU_V73 HEXAGON_CPU_TYPE_NAME("v73") > - > void hexagon_cpu_list(void); > #define cpu_list hexagon_cpu_list > > @@ -127,8 +116,6 @@ typedef struct CPUArchState { > VTCMStoreLog vtcm_log; > } CPUHexagonState; > > -OBJECT_DECLARE_CPU_TYPE(HexagonCPU, HexagonCPUClass, > HEXAGON_CPU) > - > typedef struct HexagonCPUClass { > CPUClass parent_class; > > -- > 2.41.0
Reviewed-by: Brian Cain <[email protected]>
