On Thu, 12 Dec 2019 11:43:58 +0000 Rhodri James <rho...@kynesim.co.uk> wrote:
> On 11/12/2019 21:35, Antoine Pitrou wrote: > > In any case, this will have to be judged on benchmark numbers, once > > Mark (or someone else) massages the interpreter to experiment with > > those runtime memory footprint reductions. > > This I absolutely agree with. Without evidence we're just waving our > prejudices and varied experiences at one another (for example, my > experience that the "modern processors" you were talking about have > massive caches, so memory access isn't as much of an issue as you might > think vs your experience that memory access matters more than doing a > shift-and-mask all the time). But massive caches are not that fast. L1 cache is typically very fast (3 or 4 cycles latency) but small (on the order of 64 kiB). L2 cache varies, but is generally significantly slower (typically 15 cycles latency) and medium sized (256 or 512 kiB perhaps). L3 cache is often massive (16 MiB is not uncommon) but actually quite slow (several dozens of cycles), by virtue of being large, further away and generally shared between all cores. If you have a 4-way superscalar CPU (which is an approximate description, since the level of allowed parallelism is not the same in all pipeline stages and depends on the instruction mix), during a single 15-cycle L2 cache access your CPU can issue at most 60 instructions. And during a L3 cache access there's an even larger amount of instructions that can be scheduled and executed. Regards Antoine. _______________________________________________ Python-Dev mailing list -- python-dev@python.org To unsubscribe send an email to python-dev-le...@python.org https://mail.python.org/mailman3/lists/python-dev.python.org/ Message archived at https://mail.python.org/archives/list/python-dev@python.org/message/4KA5BRDMS3ZJF4CBVITMOKVKA6PBA6NL/ Code of Conduct: http://python.org/psf/codeofconduct/
