Greetings,
As reported by visa@ (see [1]), cad/netgen is currently broken for
mips64 arch. I don't have one of those machines at my disposal, so I can
only guess, basing on the log file, that the problem is a missing prototype.
I would propose to try this patch (only tested on amd64, no regression
found in my verification environment); if it's confirmed that the port
compiles correctly on mips64 afterwards, I'll work with upstream in
order to merge it in a future release.
[1] http://build-failures.rhaalovely.net/mips64/2020-10-09/cad/netgen.log
Cheers
--
Alessandro De Laurenzis
[mailto:jus...@atlantide.mooo.com]
Web: http://www.atlantide.mooo.com
LinkedIn: http://it.linkedin.com/in/delaurenzis
Index: Makefile
===================================================================
RCS file: /cvs/ports/cad/netgen/Makefile,v
retrieving revision 1.7
diff -u -p -u -p -r1.7 Makefile
--- Makefile 3 Jul 2020 21:12:36 -0000 1.7
+++ Makefile 18 Oct 2020 13:23:07 -0000
@@ -3,7 +3,7 @@
COMMENT = tool for netlist comparison (LVS) and format manipulation
DISTNAME = netgen-1.5.138
EXTRACT_SUFX = .tgz
-REVISION = 0
+REVISION = 1
CATEGORIES = cad
Index: patches/patch-base_netgen_h
===================================================================
RCS file: patches/patch-base_netgen_h
diff -N patches/patch-base_netgen_h
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ patches/patch-base_netgen_h 18 Oct 2020 13:23:07 -0000
@@ -0,0 +1,21 @@
+$OpenBSD$
+
+Index: base/netgen.h
+--- base/netgen.h.orig
++++ base/netgen.h
+@@ -65,6 +65,15 @@ extern void AssignCircuits(char *name1, int file1, cha
+ /* flatten.c */
+ extern int PrematchLists(char *, int, char *, int);
+
++/* verilog.c */
++struct cellstack {
++ char *cellname;
++ struct cellstack *next;
++};
++
++void ReadVerilogFile(char *fname, int filenum, struct cellstack **CellStackPtr,
++ int blackbox);
++
+ /* Define (enumerate) various device classes, largely based on SPICE */
+ /* model types, mixed with some ext/sim types. */
+
Index: patches/patch-base_spice_c
===================================================================
RCS file: patches/patch-base_spice_c
diff -N patches/patch-base_spice_c
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ patches/patch-base_spice_c 18 Oct 2020 13:23:07 -0000
@@ -0,0 +1,21 @@
+$OpenBSD$
+
+Index: base/spice.c
+--- base/spice.c.orig
++++ base/spice.c
+@@ -474,15 +474,6 @@ void CleanupSubcell() {
+ }
+
+ /*------------------------------------------------------*/
+-/* Structure for stacking nested subcircuit definitions */
+-/*------------------------------------------------------*/
+-
+-struct cellstack {
+- char *cellname;
+- struct cellstack *next;
+-};
+-
+-/*------------------------------------------------------*/
+ /* Push a subcircuit name onto the stack */
+ /*------------------------------------------------------*/
+
Index: patches/patch-base_verilog_c
===================================================================
RCS file: patches/patch-base_verilog_c
diff -N patches/patch-base_verilog_c
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ patches/patch-base_verilog_c 18 Oct 2020 13:23:07 -0000
@@ -0,0 +1,17 @@
+$OpenBSD$
+
+Index: base/verilog.c
+--- base/verilog.c.orig
++++ base/verilog.c
+@@ -566,11 +566,6 @@ void CleanupModule() {
+ /* Structure for stacking nested module definitions */
+ /*------------------------------------------------------*/
+
+-struct cellstack {
+- char *cellname;
+- struct cellstack *next;
+-};
+-
+ /* Forward declarations */
+ extern void IncludeVerilog(char *, int, struct cellstack **, int);
+
