Just a note:
On 26/06/2020 16:35, Alessandro De Laurenzis wrote:
[...]
If you would like to play a bit with the port:
- make a new directory (e.g. ./qflow-trial) and copy there the enclosed
map9v3.v file;
- change to that dir and run 'qflow gui';
- in the 'synthesys preparation' tab:
* select map9v3.v as Verilog source file;
* the 'Verilog module' field will be updated automatically;
* click on 'Set stop' after every synthesis step;
If you want to avoid issues with default settings during routing step,
please select 'osu035' in the 'Technology' tab.
- click on 'Run' in the 'Preparation' row;
- then run the other steps in sequence;
- starting after the 'Placement', you'll be able to see the layout
clicking on 'Edit Layout' (type 'v' in Magic window to see the full
view).
On 21/06/2020 16:40, Tim Edwards wrote:
Hello Alessandro,
OSU 050/035/018 tech files have a proprietary license that says:
[...]
"Permission to use, copy, and modify this software and its
documentation for research and educational purposes only and without fee
or royalty is hereby granted..."
[...]
I don't know if this is too restrictive; if so, we should probably
split the package; please let me know how to proceed;
This should not be a problem. The technologies are based on the MOSIS
SCMOS technologies (see www.mosis.com). Specifically, the process
technology file for Magic is designed to be submitted to MOSIS for use
with the TSMC foundry. However, as of about two years ago, MOSIS stopped
supporting the SCMOS technology description for TSMC. Therefore, designs
using these cells are, for all intents and purposes, purely educational,
as there is no way to fabricate such a design.
Regards,
Tim
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| R. Timothy Edwards (Tim) | email: t...@opencircuitdesign.com |
| Open Circuit Design | web: http://opencircuitdesign.com |
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--
Alessandro De Laurenzis
[mailto:jus...@atlantide.mooo.com]
Web: http://www.atlantide.mooo.com
LinkedIn: http://it.linkedin.com/in/delaurenzis