Hi Alessandro, ports@, On Sat, 22 Feb 2020 08:52:09 +0100 Alessandro De Laurenzis wrote:
> Greetings, > > I posted this update proposal last week, so this is a weekly ping. > > On top of that, cwen@ submitted a patch upstream (see [1]) to unbreak > the port for archs using old GNU binutils, which has been accepted > and already merged in the code. > > So I'm attaching an updated diff jumping to the latest release (this > is the only modification added to those I described earlier). > > Charlene, please double-check and let me know. It builds fine on powerpc. While here, i've tested on amd64, and met no issues. OK cwen@ > All the best > > [1] https://github.com/RTimothyEdwards/netgen/issues/2 > > On 15/02/2020 - 18:42, Alessandro De Laurenzis wrote: > >Greetings, > > > >The attached diff updates cad/netgen to the latest release. > > > > > >What's new upstream > >=================== > >Plenty of new features and bug fixing, including: > >- Expanded the verilog parser to handle most forms of allowable wire > >and assignment statements in verilog netlists, including > >assignment of signal bundles; > >- Added support in the verilog parser for definitions anywhere in > >the code using the backtick expression; > >- A fairly large refactoring of the conditional handling code in > >the verilog parser; > >- Added handling of backslash characters in instance names in the > >JSON output; > >- added command "netgen::format " to set the output format width. > > > > > >What's new in the port > >====================== > >- updated maintainer email address; > >- we need to add "--with-distdir=${PREFIX}" to CONFIGURE_ARGS (due > >to a recent upstream change related to distributed install); > >- all other differences are trivial updates. > > > > > >Lightly tested on amd64 only. > > -- > Alessandro De Laurenzis > [mailto:[email protected]] > Web: http://www.atlantide.mooo.com > LinkedIn: http://it.linkedin.com/in/delaurenzis
