On Tue Dec 30, 2025 at 11:06:54AM +0000, Edd Barrett wrote:
> Hi,
>
> Update rizin to latest. OK?
OK rssadowski
>
> (cutter update to follow)
>
> Index: Makefile
> ===================================================================
> RCS file: /cvs/ports/devel/rizin/Makefile,v
> diff -u -p -r1.11 Makefile
> --- Makefile 21 Dec 2024 11:39:34 -0000 1.11
> +++ Makefile 12 Dec 2025 16:23:17 -0000
> @@ -4,20 +4,19 @@ ONLY_FOR_ARCHS = aarch64 amd64 i386
>
> COMMENT = free and open source reverse engineering framework
>
> -V = 0.7.2
> +V = 0.8.1
> DISTNAME = rizin-src-v${V}
> EXTRACT_SUFX = .tar.xz
> PKGNAME = rizin-${V}
> -REVISION = 1
>
> SITES =
> https://github.com/rizinorg/rizin/releases/download/v${V}/
>
> # Upstream shared lib versions are the same as the rizin release version.
> -LIBV = 1.0 # ${V}
> -.for _lib in rz_analysis rz_asm rz_bin rz_bp rz_config rz_cons rz_core \
> - rz_crypto rz_debug rz_demangler rz_diff rz_egg rz_flag rz_hash \
> - rz_il rz_io rz_lang rz_magic rz_main rz_parse rz_reg rz_search \
> - rz_sign rz_socket rz_syscall rz_type rz_util
> +LIBV = 2.0 # ${V}
> +.for _lib in rz_analysis rz_asm rz_arch rz_bin rz_bp rz_config rz_cons \
> + rz_core rz_crypto rz_debug rz_demangler rz_diff rz_egg rz_flag \
> + rz_hash rz_il rz_io rz_lang rz_magic rz_main rz_parse rz_reg \
> + rz_search rz_sign rz_socket rz_syscall rz_type rz_util
> SHARED_LIBS+= ${_lib} ${LIBV}
> .endfor
>
> @@ -50,8 +49,9 @@ LIB_DEPENDS = devel/capstone/main \
> BUILD_DEPENDS = textproc/py-yaml
>
> # The release tarball is vendored and has a lot of dependencies bundled. We
> -# "unbundle" them where possible with `-Duse_sys_*=enabled`. When updating,
> the
> -# port, check `meson.build` for new dependencies that cen be unbundled.
> +# "unbundle" them where possible with `-Duse_sys_*=enabled`. When updating,
> +# check the report printed at the end of the configure stage for other deps
> +# that could be unbundled.
> #
> # We don't use the system treesitter, as upstream inform me that rizin is
> quite
> # sensitive to treesitter versions.
> Index: distinfo
> ===================================================================
> RCS file: /cvs/ports/devel/rizin/distinfo,v
> diff -u -p -r1.3 distinfo
> --- distinfo 14 Apr 2024 15:39:33 -0000 1.3
> +++ distinfo 11 Dec 2025 13:49:28 -0000
> @@ -1,2 +1,2 @@
> -SHA256 (rizin-src-v0.7.2.tar.xz) =
> 6vnkOl2heENHp0ZyTllDj0oWlNyh5ipQCSAJ8BcuH2w=
> -SIZE (rizin-src-v0.7.2.tar.xz) = 18601700
> +SHA256 (rizin-src-v0.8.1.tar.xz) =
> 7yseZSXX3DasQ1JblWdJwcyge/F8H+2LZkAtggEKTsI=
> +SIZE (rizin-src-v0.8.1.tar.xz) = 21334856
> Index: patches/patch-librz_analysis_p_analysis_mips_cs_c
> ===================================================================
> RCS file: patches/patch-librz_analysis_p_analysis_mips_cs_c
> diff -N patches/patch-librz_analysis_p_analysis_mips_cs_c
> --- patches/patch-librz_analysis_p_analysis_mips_cs_c 14 Apr 2024 15:39:33
> -0000 1.2
> +++ /dev/null 1 Jan 1970 00:00:00 -0000
> @@ -1,94 +0,0 @@
> -Our capstone port renames a mips struct member to avoid a name clash.
> -
> -Index: librz/analysis/p/analysis_mips_cs.c
> ---- librz/analysis/p/analysis_mips_cs.c.orig
> -+++ librz/analysis/p/analysis_mips_cs.c
> -@@ -9,14 +9,14 @@
> - static ut64 t9_pre = UT64_MAX;
> - // http://www.mrc.uidaho.edu/mrc/people/jff/digital/MIPSir.html
> -
> --#define OPERAND(x) insn->detail->mips.operands[x]
> --#define REGID(x) insn->detail->mips.operands[x].reg
> --#define REG(x) cs_reg_name(*handle, insn->detail->mips.operands[x].reg)
> --#define IMM(x) insn->detail->mips.operands[x].imm
> --#define MEMBASE(x) cs_reg_name(*handle,
> insn->detail->mips.operands[x].mem.base)
> --#define MEMINDEX(x) insn->detail->mips.operands[x].mem.index
> --#define MEMDISP(x) insn->detail->mips.operands[x].mem.disp
> --#define OPCOUNT() insn->detail->mips.op_count
> -+#define OPERAND(x) insn->detail->mipsen.operands[x]
> -+#define REGID(x) insn->detail->mipsen.operands[x].reg
> -+#define REG(x) cs_reg_name(*handle,
> insn->detail->mipsen.operands[x].reg)
> -+#define IMM(x) insn->detail->mipsen.operands[x].imm
> -+#define MEMBASE(x) cs_reg_name(*handle,
> insn->detail->mipsen.operands[x].mem.base)
> -+#define MEMINDEX(x) insn->detail->mipsen.operands[x].mem.index
> -+#define MEMDISP(x) insn->detail->mipsen.operands[x].mem.disp
> -+#define OPCOUNT() insn->detail->mipsen.op_count
> - // TODO scale and disp
> -
> - #define SET_VAL(op, i) \
> -@@ -132,7 +132,7 @@ static void opex(RzStrBuf *buf, csh handle, cs_insn *i
> - }
> - pj_o(pj);
> - pj_ka(pj, "operands");
> -- cs_mips *x = &insn->detail->mips;
> -+ cs_mips *x = &insn->detail->mipsen;
> - for (i = 0; i < x->op_count; i++) {
> - cs_mips_op *op = x->operands + i;
> - pj_o(pj);
> -@@ -168,30 +168,30 @@ static void opex(RzStrBuf *buf, csh handle, cs_insn *i
> -
> - static const char *arg(csh *handle, cs_insn *insn, char *buf, int n) {
> - *buf = 0;
> -- switch (insn->detail->mips.operands[n].type) {
> -+ switch (insn->detail->mipsen.operands[n].type) {
> - case MIPS_OP_INVALID:
> - break;
> - case MIPS_OP_REG:
> - sprintf(buf, "%s",
> - cs_reg_name(*handle,
> -- insn->detail->mips.operands[n].reg));
> -+ insn->detail->mipsen.operands[n].reg));
> - break;
> - case MIPS_OP_IMM: {
> -- st64 x = (st64)insn->detail->mips.operands[n].imm;
> -+ st64 x = (st64)insn->detail->mipsen.operands[n].imm;
> - sprintf(buf, "%" PFMT64d, x);
> - } break;
> - case MIPS_OP_MEM: {
> -- int disp = insn->detail->mips.operands[n].mem.disp;
> -+ int disp = insn->detail->mipsen.operands[n].mem.disp;
> - if (disp < 0) {
> - sprintf(buf, "%" PFMT64d ",%s,-",
> -- (ut64)-insn->detail->mips.operands[n].mem.disp,
> -+
> (ut64)-insn->detail->mipsen.operands[n].mem.disp,
> - cs_reg_name(*handle,
> --
> insn->detail->mips.operands[n].mem.base));
> -+
> insn->detail->mipsen.operands[n].mem.base));
> - } else {
> - sprintf(buf, "0x%" PFMT64x ",%s,+",
> -- (ut64)insn->detail->mips.operands[n].mem.disp,
> -+ (ut64)insn->detail->mipsen.operands[n].mem.disp,
> - cs_reg_name(*handle,
> --
> insn->detail->mips.operands[n].mem.base));
> -+
> insn->detail->mipsen.operands[n].mem.base));
> - }
> - } break;
> - }
> -@@ -209,7 +209,7 @@ static int analyze_op_esil(RzAnalysis *a, RzAnalysisOp
> -
> - if (insn) {
> - // caching operands
> -- for (i = 0; i < insn->detail->mips.op_count && i < 8; i++) {
> -+ for (i = 0; i < insn->detail->mipsen.op_count && i < 8; i++) {
> - *str[i] = 0;
> - ARG(i);
> - }
> -@@ -1049,7 +1049,7 @@ static int analyze_op(RzAnalysis *analysis, RzAnalysis
> - op->type = RZ_ANALYSIS_OP_TYPE_RJMP;
> - op->delay = 1;
> - // register is $ra, so jmp is a return
> -- if (insn->detail->mips.operands[0].reg == MIPS_REG_RA) {
> -+ if (insn->detail->mipsen.operands[0].reg == MIPS_REG_RA) {
> - op->type = RZ_ANALYSIS_OP_TYPE_RET;
> - t9_pre = UT64_MAX;
> - }
> Index: patches/patch-librz_arch_isa_mips_mips_esil_c
> ===================================================================
> RCS file: patches/patch-librz_arch_isa_mips_mips_esil_c
> diff -N patches/patch-librz_arch_isa_mips_mips_esil_c
> --- /dev/null 1 Jan 1970 00:00:00 -0000
> +++ patches/patch-librz_arch_isa_mips_mips_esil_c 12 Dec 2025 14:36:24
> -0000
> @@ -0,0 +1,68 @@
> +Our capstone port renames a mips struct member to avoid a name clash.
> +
> +Index: librz/arch/isa/mips/mips_esil.c
> +--- librz/arch/isa/mips/mips_esil.c.orig
> ++++ librz/arch/isa/mips/mips_esil.c
> +@@ -5,10 +5,10 @@
> + #include <capstone/capstone.h>
> + #include <capstone/mips.h>
> +
> +-#define OPCOUNT() insn->detail->mips.op_count
> +-#define REGID(x) insn->detail->mips.operands[x].reg
> +-#define REG(x) cs_reg_name(*handle, insn->detail->mips.operands[x].reg)
> +-#define IMM(x) insn->detail->mips.operands[x].imm
> ++#define OPCOUNT() insn->detail->mipsen.op_count
> ++#define REGID(x) insn->detail->mipsen.operands[x].reg
> ++#define REG(x) cs_reg_name(*handle, insn->detail->mipsen.operands[x].reg)
> ++#define IMM(x) insn->detail->mipsen.operands[x].imm
> +
> + // ESIL macros:
> + // put the sign bit on the stack
> +@@ -80,30 +80,30 @@ static inline void es_add_ck(RzAnalysisOp *op, const c
> +
> + static const char *arg(csh *handle, cs_insn *insn, char *buf, int n) {
> + *buf = 0;
> +- switch (insn->detail->mips.operands[n].type) {
> ++ switch (insn->detail->mipsen.operands[n].type) {
> + case MIPS_OP_INVALID:
> + break;
> + case MIPS_OP_REG:
> + sprintf(buf, "%s",
> + cs_reg_name(*handle,
> +- insn->detail->mips.operands[n].reg));
> ++ insn->detail->mipsen.operands[n].reg));
> + break;
> + case MIPS_OP_IMM: {
> +- st64 x = (st64)insn->detail->mips.operands[n].imm;
> ++ st64 x = (st64)insn->detail->mipsen.operands[n].imm;
> + sprintf(buf, "%" PFMT64d, x);
> + } break;
> + case MIPS_OP_MEM: {
> +- int disp = insn->detail->mips.operands[n].mem.disp;
> ++ int disp = insn->detail->mipsen.operands[n].mem.disp;
> + if (disp < 0) {
> + sprintf(buf, "%" PFMT64d ",%s,-",
> +- (ut64)-insn->detail->mips.operands[n].mem.disp,
> ++
> (ut64)-insn->detail->mipsen.operands[n].mem.disp,
> + cs_reg_name(*handle,
> +-
> insn->detail->mips.operands[n].mem.base));
> ++
> insn->detail->mipsen.operands[n].mem.base));
> + } else {
> + sprintf(buf, "0x%" PFMT64x ",%s,+",
> +- (ut64)insn->detail->mips.operands[n].mem.disp,
> ++ (ut64)insn->detail->mipsen.operands[n].mem.disp,
> + cs_reg_name(*handle,
> +-
> insn->detail->mips.operands[n].mem.base));
> ++
> insn->detail->mipsen.operands[n].mem.base));
> + }
> + } break;
> + }
> +@@ -123,7 +123,7 @@ RZ_IPI int analyze_op_esil(RzAnalysis *a, RzAnalysisOp
> + }
> +
> + // caching operands
> +- for (int i = 0; i < insn->detail->mips.op_count && i < 8; i++) {
> ++ for (int i = 0; i < insn->detail->mipsen.op_count && i < 8; i++) {
> + *str[i] = 0;
> + ARG(i);
> + }
> Index: patches/patch-librz_arch_isa_mips_mips_internal_h
> ===================================================================
> RCS file: patches/patch-librz_arch_isa_mips_mips_internal_h
> diff -N patches/patch-librz_arch_isa_mips_mips_internal_h
> --- /dev/null 1 Jan 1970 00:00:00 -0000
> +++ patches/patch-librz_arch_isa_mips_mips_internal_h 12 Dec 2025 15:11:28
> -0000
> @@ -0,0 +1,30 @@
> +Index: librz/arch/isa/mips/mips_internal.h
> +--- librz/arch/isa/mips/mips_internal.h.orig
> ++++ librz/arch/isa/mips/mips_internal.h
> +@@ -8,16 +8,16 @@
> + #include <capstone/capstone.h>
> + #include <capstone/mips.h>
> +
> +-#define OPERAND(x) insn->detail->mips.operands[x]
> +-#define REGID(x) insn->detail->mips.operands[x].reg
> +-#define IS_REG(x) (insn->detail->mips.operands[x].type == MIPS_OP_REG)
> +-#define REG(x) cs_reg_name(*handle,
> insn->detail->mips.operands[x].reg)
> +-#define IS_IMM(x) (insn->detail->mips.operands[x].type == MIPS_OP_IMM)
> +-#define IMM(x) insn->detail->mips.operands[x].imm
> +-#define IS_MEM(x) (insn->detail->mips.operands[x].type == MIPS_OP_MEM)
> +-#define MEMBASE(x) cs_reg_name(*handle,
> insn->detail->mips.operands[x].mem.base)
> +-#define MEMOFFSET(x) (st64) insn->detail->mips.operands[x].mem.disp
> +-#define OPCOUNT() insn->detail->mips.op_count
> ++#define OPERAND(x) insn->detail->mipsen.operands[x]
> ++#define REGID(x) insn->detail->mipsen.operands[x].reg
> ++#define IS_REG(x) (insn->detail->mipsen.operands[x].type == MIPS_OP_REG)
> ++#define REG(x) cs_reg_name(*handle,
> insn->detail->mipsen.operands[x].reg)
> ++#define IS_IMM(x) (insn->detail->mipsen.operands[x].type == MIPS_OP_IMM)
> ++#define IMM(x) insn->detail->mipsen.operands[x].imm
> ++#define IS_MEM(x) (insn->detail->mipsen.operands[x].type == MIPS_OP_MEM)
> ++#define MEMBASE(x) cs_reg_name(*handle,
> insn->detail->mipsen.operands[x].mem.base)
> ++#define MEMOFFSET(x) (st64) insn->detail->mipsen.operands[x].mem.disp
> ++#define OPCOUNT() insn->detail->mipsen.op_count
> +
> + RZ_IPI RzILOpEffect *mips_il(RZ_NONNULL const csh *handle, RZ_NONNULL const
> cs_insn *insn, const ut32 gprlen);
> + RZ_IPI RzAnalysisILConfig *mips_il_config(RzAnalysis *analysis);
> Index: patches/patch-librz_arch_p_analysis_analysis_mips_cs_c
> ===================================================================
> RCS file: patches/patch-librz_arch_p_analysis_analysis_mips_cs_c
> diff -N patches/patch-librz_arch_p_analysis_analysis_mips_cs_c
> --- /dev/null 1 Jan 1970 00:00:00 -0000
> +++ patches/patch-librz_arch_p_analysis_analysis_mips_cs_c 12 Dec 2025
> 15:12:39 -0000
> @@ -0,0 +1,21 @@
> +Index: librz/arch/p/analysis/analysis_mips_cs.c
> +--- librz/arch/p/analysis/analysis_mips_cs.c.orig
> ++++ librz/arch/p/analysis/analysis_mips_cs.c
> +@@ -61,7 +61,7 @@ static void opex(RzStrBuf *buf, csh handle, cs_insn *i
> + }
> + pj_o(pj);
> + pj_ka(pj, "operands");
> +- cs_mips *x = &insn->detail->mips;
> ++ cs_mips *x = &insn->detail->mipsen;
> + for (i = 0; i < x->op_count; i++) {
> + cs_mips_op *op = x->operands + i;
> + pj_o(pj);
> +@@ -767,7 +767,7 @@ static int mips_analyze_op(RzAnalysis *analysis, RzAna
> + }
> + op->type = RZ_ANALYSIS_OP_TYPE_RJMP;
> + // register is $ra, so jmp is a return
> +- if (insn->detail->mips.operands[0].reg == MIPS_REG_RA) {
> ++ if (insn->detail->mipsen.operands[0].reg == MIPS_REG_RA) {
> + op->type = RZ_ANALYSIS_OP_TYPE_RET;
> + ctx->t9_pre = UT64_MAX;
> + }
> Index: patches/patch-librz_debug_p_native_bsd_bsd_debug_c
> ===================================================================
> RCS file: patches/patch-librz_debug_p_native_bsd_bsd_debug_c
> diff -N patches/patch-librz_debug_p_native_bsd_bsd_debug_c
> --- patches/patch-librz_debug_p_native_bsd_bsd_debug_c 26 Jul 2024
> 08:37:41 -0000 1.1
> +++ /dev/null 1 Jan 1970 00:00:00 -0000
> @@ -1,30 +0,0 @@
> -Index: librz/debug/p/native/bsd/bsd_debug.c
> ---- librz/debug/p/native/bsd/bsd_debug.c.orig
> -+++ librz/debug/p/native/bsd/bsd_debug.c
> -@@ -211,16 +211,19 @@ RzDebugInfo *bsd_info(RzDebug *dbg, const char *arg) {
> - rdi->gid = kp->p__pgid;
> - rdi->exe = strdup(kp->p_comm);
> -
> -- rdi->status = RZ_DBG_PROC_STOP;
> --
> -- if (kp->p_psflags & PS_ZOMBIE) {
> -- rdi->status = RZ_DBG_PROC_ZOMBIE;
> -- } else if (kp->p_psflags & PS_STOPPED) {
> -+ switch (kp->p_stat) {
> -+ case SDEAD:
> -+ rdi->status = RZ_DBG_PROC_DEAD;
> -+ break;
> -+ case SSTOP:
> - rdi->status = RZ_DBG_PROC_STOP;
> -- } else if (kp->p_psflags & PS_PPWAIT) {
> -+ break;
> -+ case SSLEEP:
> - rdi->status = RZ_DBG_PROC_SLEEP;
> -- } else if ((kp->p_psflags & PS_EXEC) || (kp->p_psflags &
> PS_INEXEC)) {
> -+ break;
> -+ default:
> - rdi->status = RZ_DBG_PROC_RUN;
> -+ break;
> - }
> - }
> -
> Index: patches/patch-meson_build
> ===================================================================
> RCS file: /cvs/ports/devel/rizin/patches/patch-meson_build,v
> diff -u -p -r1.1 patch-meson_build
> --- patches/patch-meson_build 14 Apr 2024 15:39:33 -0000 1.1
> +++ patches/patch-meson_build 12 Dec 2025 14:11:55 -0000
> @@ -6,7 +6,7 @@ Error at runtime if you leave it on:
> Index: meson.build
> --- meson.build.orig
> +++ meson.build
> -@@ -197,7 +197,7 @@ endif
> +@@ -212,7 +212,7 @@ endif
>
> # Handle PCRE2
> cpu_jit_supported = [ 'aarch64', 'arm', 'mips', 'mips64', 'ppc', 'ppc64',
> 'riscv32', 'riscv64', 's390x', 'x86', 'x86_64' ]
> Index: pkg/PLIST
> ===================================================================
> RCS file: /cvs/ports/devel/rizin/pkg/PLIST,v
> diff -u -p -r1.3 PLIST
> --- pkg/PLIST 14 Apr 2024 15:39:33 -0000 1.3
> +++ pkg/PLIST 12 Dec 2025 15:20:39 -0000
> @@ -12,6 +12,7 @@
> include/librz/
> include/librz/rz_agraph.h
> include/librz/rz_analysis.h
> +include/librz/rz_arch.h
> include/librz/rz_asm.h
> include/librz/rz_basefind.h
> include/librz/rz_bin.h
> @@ -28,7 +29,9 @@ include/librz/rz_constructor.h
> include/librz/rz_core.h
> include/librz/rz_crypto/
> include/librz/rz_crypto.h
> +include/librz/rz_crypto/rz_aes.h
> include/librz/rz_crypto/rz_des.h
> +include/librz/rz_crypto/rz_sm4.h
> include/librz/rz_debug.h
> include/librz/rz_demangler.h
> include/librz/rz_diff.h
> @@ -69,6 +72,7 @@ include/librz/rz_pdb.h
> include/librz/rz_platform.h
> include/librz/rz_project.h
> include/librz/rz_reg.h
> +include/librz/rz_rop.h
> include/librz/rz_search.h
> include/librz/rz_sign.h
> include/librz/rz_skiplist.h
> @@ -86,6 +90,9 @@ include/librz/rz_util.h
> include/librz/rz_util/ht_inc.h
> include/librz/rz_util/ht_pp.h
> include/librz/rz_util/ht_pu.h
> +include/librz/rz_util/ht_sp.h
> +include/librz/rz_util/ht_ss.h
> +include/librz/rz_util/ht_su.h
> include/librz/rz_util/ht_up.h
> include/librz/rz_util/ht_uu.h
> include/librz/rz_util/rz_alloc.h
> @@ -129,6 +136,7 @@ include/librz/rz_util/rz_range.h
> include/librz/rz_util/rz_rbtree.h
> include/librz/rz_util/rz_regex.h
> include/librz/rz_util/rz_serialize.h
> +include/librz/rz_util/rz_set.h
> include/librz/rz_util/rz_signal.h
> include/librz/rz_util/rz_spaces.h
> include/librz/rz_util/rz_stack.h
> @@ -145,12 +153,12 @@ include/librz/rz_util/rz_th_ht.h
> include/librz/rz_util/rz_time.h
> include/librz/rz_util/rz_tree.h
> include/librz/rz_util/rz_uleb128.h
> +include/librz/rz_util/rz_unicode.h
> include/librz/rz_util/rz_utf16.h
> include/librz/rz_util/rz_utf32.h
> include/librz/rz_util/rz_utf8.h
> include/librz/rz_util/rz_version.h
> include/librz/rz_util/rz_x509.h
> -include/librz/rz_util/set.h
> include/librz/rz_vector.h
> include/librz/rz_windows.h
> include/librz/rz_windows_heap.h
> @@ -158,7 +166,6 @@ include/librz/sdb/
> include/librz/sdb/buffer.h
> include/librz/sdb/cdb.h
> include/librz/sdb/cdb_make.h
> -include/librz/sdb/ls.h
> include/librz/sdb/sdb.h
> include/librz/sdb/sdbht.h
> include/librz/sflib/
> @@ -195,10 +202,8 @@ include/librz/sflib/linux-x86-64/sfsysca
> include/librz/sflib/linux-x86-64/sfsysnr.h
> lib/cmake/Rizin/
> lib/cmake/Rizin/RizinConfig.cmake
> -lib/cmake/rz_analysis/
> -lib/cmake/rz_analysis/rz_analysisConfig.cmake
> -lib/cmake/rz_asm/
> -lib/cmake/rz_asm/rz_asmConfig.cmake
> +lib/cmake/rz_arch/
> +lib/cmake/rz_arch/rz_archConfig.cmake
> lib/cmake/rz_bin/
> lib/cmake/rz_bin/rz_binConfig.cmake
> lib/cmake/rz_bp/
> @@ -233,8 +238,6 @@ lib/cmake/rz_magic/
> lib/cmake/rz_magic/rz_magicConfig.cmake
> lib/cmake/rz_main/
> lib/cmake/rz_main/rz_mainConfig.cmake
> -lib/cmake/rz_parse/
> -lib/cmake/rz_parse/rz_parseConfig.cmake
> lib/cmake/rz_reg/
> lib/cmake/rz_reg/rz_regConfig.cmake
> lib/cmake/rz_search/
> @@ -249,8 +252,7 @@ lib/cmake/rz_type/
> lib/cmake/rz_type/rz_typeConfig.cmake
> lib/cmake/rz_util/
> lib/cmake/rz_util/rz_utilConfig.cmake
> -@lib lib/librz_analysis.so.${LIBrz_analysis_VERSION}
> -@lib lib/librz_asm.so.${LIBrz_asm_VERSION}
> +@lib lib/librz_arch.so.${LIBrz_arch_VERSION}
> @lib lib/librz_bin.so.${LIBrz_bin_VERSION}
> @lib lib/librz_bp.so.${LIBrz_bp_VERSION}
> @lib lib/librz_config.so.${LIBrz_config_VERSION}
> @@ -268,7 +270,6 @@ lib/cmake/rz_util/rz_utilConfig.cmake
> @lib lib/librz_lang.so.${LIBrz_lang_VERSION}
> @lib lib/librz_magic.so.${LIBrz_magic_VERSION}
> @lib lib/librz_main.so.${LIBrz_main_VERSION}
> -@lib lib/librz_parse.so.${LIBrz_parse_VERSION}
> @lib lib/librz_reg.so.${LIBrz_reg_VERSION}
> @lib lib/librz_search.so.${LIBrz_search_VERSION}
> @lib lib/librz_sign.so.${LIBrz_sign_VERSION}
> @@ -276,8 +277,7 @@ lib/cmake/rz_util/rz_utilConfig.cmake
> @lib lib/librz_syscall.so.${LIBrz_syscall_VERSION}
> @lib lib/librz_type.so.${LIBrz_type_VERSION}
> @lib lib/librz_util.so.${LIBrz_util_VERSION}
> -lib/pkgconfig/rz_analysis.pc
> -lib/pkgconfig/rz_asm.pc
> +lib/pkgconfig/rz_arch.pc
> lib/pkgconfig/rz_bin.pc
> lib/pkgconfig/rz_bp.pc
> lib/pkgconfig/rz_config.pc
> @@ -295,7 +295,6 @@ lib/pkgconfig/rz_io.pc
> lib/pkgconfig/rz_lang.pc
> lib/pkgconfig/rz_magic.pc
> lib/pkgconfig/rz_main.pc
> -lib/pkgconfig/rz_parse.pc
> lib/pkgconfig/rz_reg.pc
> lib/pkgconfig/rz_search.pc
> lib/pkgconfig/rz_sign.pc
> @@ -315,6 +314,12 @@ lib/pkgconfig/rz_util.pc
> @man man/man1/rz-sign.1
> @man man/man7/rz-esil.7
> share/rizin/
> +share/rizin/arch/
> +share/rizin/arch/platforms/
> +share/rizin/arch/platforms/arm-arm1176-bcm2835.sdb
> +share/rizin/arch/platforms/arm-cortexA72-bcm2711.sdb
> +share/rizin/arch/platforms/arm-cortexA8-omap3430.sdb
> +share/rizin/arch/platforms/x86-generic-generic.sdb
> share/rizin/asm/
> share/rizin/asm/cpus/
> share/rizin/asm/cpus/avr-ATTiny48.sdb
> @@ -329,11 +334,6 @@ share/rizin/asm/cpus/avr-ATmega640.sdb
> share/rizin/asm/cpus/avr-ATmega8.sdb
> share/rizin/asm/cpus/avr-ATmega88.sdb
> share/rizin/asm/cpus/avr-ATxmega128a4u.sdb
> -share/rizin/asm/platforms/
> -share/rizin/asm/platforms/arm-arm1176-bcm2835.sdb
> -share/rizin/asm/platforms/arm-cortexA72-bcm2711.sdb
> -share/rizin/asm/platforms/arm-cortexA8-omap3430.sdb
> -share/rizin/asm/platforms/x86-generic-generic.sdb
> share/rizin/cons/
> share/rizin/cons/ayu
> share/rizin/cons/basic
> @@ -591,6 +591,8 @@ share/rizin/opcodes/pic18c.sdb
> share/rizin/opcodes/ppc.sdb
> share/rizin/opcodes/propeller.sdb
> share/rizin/opcodes/riscv.sdb
> +share/rizin/opcodes/rl78.sdb
> +share/rizin/opcodes/rx.sdb
> share/rizin/opcodes/sh.sdb
> share/rizin/opcodes/sparc.sdb
> share/rizin/opcodes/sysz.sdb
>
> --
> Best Regards
> Edd Barrett
>
> https://www.theunixzoo.co.uk
>
