On 2/19/25 1:21 AM, Benjamin Stürz wrote:
On 2/18/25 9:50 PM, Benjamin Stürz wrote:
Hi ports@,
this is an update to yosys v0.50.
Before this can be imported,
both devel/cxxopts and cad/abc have to be done.
I have tested this on my personal CPU project [1]
and it works as intended.
I'm currenyly finishing porting nextpnr [2] and prjtrellis [3],
which I'll also submit soon.
[1] https://got.stuerz.xyz/?action=summary&path=cpu.git
[2] https://github.com/YosysHQ/nextpnr
[3] https://github.com/YosysHQ/prjtrellis
Patch:
Thanks to sthen@, I found out that DIST_TUPLE exists.
New patch:
diff e738812379d8372df42121c8701033afc1340fd2
d69b0dc40cfeae6bda6ba0ff0bd325c67375f48b
commit - e738812379d8372df42121c8701033afc1340fd2
commit + d69b0dc40cfeae6bda6ba0ff0bd325c67375f48b
blob - c4015435577a6e71375707d30559c6e4e9a8977f
blob + d0f274f310d176009b5287c0de0cfb4b6df6422f
--- cad/yosys/Makefile
+++ cad/yosys/Makefile
@@ -1,16 +1,15 @@
COMMENT = framework for Verilog RTL synthesis
-DISTNAME = yosys-0.9pl4081
-REVISION = 4
+V = 0.50
+DISTNAME = yosys-$V
-GH_ACCOUNT = YosysHQ
-GH_PROJECT = yosys
-GH_COMMIT = 25de8faf10157ab0cb40f77c7cbf3143527c598e
-
CATEGORIES = cad
HOMEPAGE = http://www.clifford.at/yosys/
MAINTAINER = Alessandro De Laurenzis <jus...@atlantide.mooo.com>
+DIST_TUPLE = github YosysHQ yosys v$V . \
+ github jarro2783 cxxopts v3.2.0 libs/cxxopts
+
# ISC (yosys), MIT (MiniSat)
PERMIT_PACKAGE = Yes
blob - 97997594a63f985deba834da40da2a836d957ec1
blob + 9df5e3c4d33ec0813a911ba986230a49c340bb1d
--- cad/yosys/distinfo
+++ cad/yosys/distinfo
@@ -1,2 +1,4 @@
-SHA256 (yosys-0.9pl4081-25de8faf.tar.gz) =
ProWZDm6xHgXlv8M1zJn+b4zrgGUIUpap6YV5MrdKRM=
-SIZE (yosys-0.9pl4081-25de8faf.tar.gz) = 1976189
+SHA256 (YosysHQ-yosys-v0.50.tar.gz) =
X+kiSxRdD6QPLS7I8upwB14AvPoNnG9PRcrsXF9yEzQ=
+SHA256 (jarro2783-cxxopts-v3.2.0.tar.gz) =
n0P6lyUy5d9sX9WtD1usYGzexUHMrxcyRj2AcLu38Ds=
+SIZE (YosysHQ-yosys-v0.50.tar.gz) = 3266956
+SIZE (jarro2783-cxxopts-v3.2.0.tar.gz) = 160534
blob - b18023bc8a3145160949c20a27bb4ba956096ab9
blob + 55745dc407b4fd5dbb8d40a952adb58d5cd55425
--- cad/yosys/patches/patch-Makefile
+++ cad/yosys/patches/patch-Makefile
@@ -1,32 +1,12 @@
Index: Makefile
--- Makefile.orig
+++ Makefile
-@@ -85,7 +85,7 @@ all: top-all
- YOSYS_SRC := $(dir $(firstword $(MAKEFILE_LIST)))
+@@ -97,7 +97,7 @@ YOSYS_SRC := $(dir $(firstword $(MAKEFILE_LIST)))
VPATH := $(YOSYS_SRC)
-
+
+ CXXSTD ?= c++17
-CXXFLAGS := $(CXXFLAGS) -Wall -Wextra -ggdb -I. -I"$(YOSYS_SRC)" -MD
-MP -D_YOSYS_ -fPIC -I$(PREFIX)/include
+CXXFLAGS := $(CXXFLAGS) -Wall -Wextra -I. -I"$(YOSYS_SRC)" -MD -MP
-D_YOSYS_ -fPIC -I$(PREFIX)/include
- LDLIBS := $(LDLIBS) -lstdc++ -lm
- PLUGIN_LDFLAGS :=
-
-@@ -349,6 +349,10 @@ else ifneq ($(CONFIG),none)
- $(error Invalid CONFIG setting '$(CONFIG)'. Valid values: clang, gcc,
gcc-4.8, emcc, mxe, msys2-32, msys2-64)
- endif
-
-+ifeq ($(OS), OpenBSD)
-+LDLIBS := $(filter-out -lrt, $(LDLIBS))
-+endif
-+
- ifeq ($(ENABLE_LIBYOSYS),1)
- TARGETS += libyosys.so
- endif
-@@ -439,7 +443,7 @@ endif
- ifeq ($(ENABLE_PLUGINS),1)
- CXXFLAGS += $(shell PKG_CONFIG_PATH=$(PKG_CONFIG_PATH) $(PKG_CONFIG)
--silence-errors --cflags libffi) -DYOSYS_ENABLE_PLUGINS
- LDLIBS += $(shell PKG_CONFIG_PATH=$(PKG_CONFIG_PATH) $(PKG_CONFIG)
--silence-errors --libs libffi || echo -lffi)
--ifneq ($(OS), FreeBSD)
-+ifneq ($(OS), $(filter $(OS), FreeBSD OpenBSD))
- LDLIBS += -ldl
- endif
- endif
+ LIBS := $(LIBS) -lstdc++ -lm
+ PLUGIN_LINKFLAGS :=
+ PLUGIN_LIBS :=
blob - f929a46a7f89bb020d96242fc00a725cf2ed4f5a (mode 644)
blob + /dev/null
--- cad/yosys/patches/patch-kernel_yosys_cc
+++ /dev/null
@@ -1,26 +0,0 @@
-Index: kernel/yosys.cc
---- kernel/yosys.cc.orig
-+++ kernel/yosys.cc
-@@ -69,6 +69,10 @@
- #endif
- #endif
-
-+#ifdef __OpenBSD__
-+# include <sys/wait.h>
-+#endif
-+
- #include <limits.h>
- #include <errno.h>
-
-@@ -787,6 +791,11 @@ std::string proc_self_dirname()
- path.assign(buffer, buflen);
- free(buffer);
- return path;
-+}
-+#elif defined(__OpenBSD__)
-+std::string proc_self_dirname()
-+{
-+ return "${PREFIX}/bin/";
- }
- #elif defined(__APPLE__)
- std::string proc_self_dirname()
blob - /dev/null
blob + 187ac78c591a193a0c2a6550c3df404630e101b4 (mode 644)
--- /dev/null
+++ cad/yosys/patches/patch-kernel_driver_cc
@@ -0,0 +1,12 @@
+Index: kernel/driver.cc
+--- kernel/driver.cc.orig
++++ kernel/driver.cc
+@@ -20,7 +20,7 @@
+ #include "kernel/yosys.h"
+ #include "kernel/hashlib.h"
+ #include "libs/sha1/sha1.h"
+-#include "libs/cxxopts/include/cxxopts.hpp"
++#include <cxxopts.hpp>
+ #include <iostream>
+
+ #ifdef YOSYS_ENABLE_READLINE
blob - e7a9b5a12e2c28b22d1cdca13b4560842ad8a15b
blob + 32e7d2a02004960223c7c4807c511aa7049124c6
--- cad/yosys/patches/patch-passes_cmds_show_cc
+++ cad/yosys/patches/patch-passes_cmds_show_cc
@@ -1,12 +1,12 @@
Index: passes/cmds/show.cc
--- passes/cmds/show.cc.orig
+++ passes/cmds/show.cc
-@@ -880,7 +880,7 @@ struct ShowPass : public Pass {
- #ifdef __APPLE__
- std::string cmd = stringf("ps -fu %d | grep -q '[ ]%s' || xdot '%s'
%s", getuid(), dot_file.c_str(), dot_file.c_str(), background.c_str());
- #else
-- std::string cmd = stringf("{ test -f '%s.pid' && fuser -s '%s.pid'
2> /dev/null; } || ( echo $$ >&3; exec xdot '%s'; ) 3> '%s.pid' %s",
dot_file.c_str(), dot_file.c_str(), dot_file.c_str(), dot_file.c_str(),
background.c_str());
-+ std::string cmd = stringf("test -f '%s.pid' -a -n \"`fuser '%s.pid'
2>/dev/null`\" || ( echo $$ >&3; exec xdot '%s'; ) 3> '%s.pid' %s",
dot_file.c_str(), dot_file.c_str(), dot_file.c_str(), dot_file.c_str(),
background.c_str());
- #endif
- log("Exec: %s\n", cmd.c_str());
- if (run_command(cmd) != 0)
+@@ -957,6 +957,8 @@ struct ShowPass : public Pass {
+ if (format.empty()) {
+ #ifdef __APPLE__
+ std::string cmd = stringf("ps -fu %d | grep -q '[ ]%s' || xdot
'%s' %s", getuid(), dot_file.c_str(), dot_file.c_str(), background.c_str());
++ #elif defined(__OpenBSD__)
++ std::string cmd = stringf("test -f '%s.pid' -a -n \"`fuser
'%s.pid' 2>/dev/null`\" || ( echo $$ >&3; exec xdot '%s'; ) 3> '%s.pid'
%s", dot_file.c_str(), dot_file.c_str(), dot_file.c_str(),
dot_file.c_str(), background.c_str());
+ #else
+ std::string cmd = stringf("{ test -f '%s.pid' && fuser -s '%s.pid'
2> /dev/null; } || ( echo $$ >&3; exec xdot '%s'; ) 3> '%s.pid' %s",
dot_file.c_str(), dot_file.c_str(), dot_file.c_str(), dot_file.c_str(),
background.c_str());
+ #endif
blob - 94ccbaa7a3a25d926b6f050047c986d5006e3064
blob + 054e0ad011ba3765bcb727fd4e87033e93b9db78
--- cad/yosys/pkg/PLIST
+++ cad/yosys/pkg/PLIST
@@ -2,6 +2,7 @@
bin/yosys-config
@bin bin/yosys-filterlib
bin/yosys-smtbmc
+bin/yosys-witness
share/yosys/
share/yosys/abc9_map.v
share/yosys/abc9_model.v
@@ -13,15 +14,21 @@ share/yosys/achronix/speedster22i/cells_sim.v
share/yosys/adff2dff.v
share/yosys/anlogic/
share/yosys/anlogic/arith_map.v
+share/yosys/anlogic/brams.txt
+share/yosys/anlogic/brams_map.v
share/yosys/anlogic/cells_map.v
share/yosys/anlogic/cells_sim.v
share/yosys/anlogic/eagle_bb.v
-share/yosys/anlogic/lutram_init_16x4.vh
share/yosys/anlogic/lutrams.txt
share/yosys/anlogic/lutrams_map.v
share/yosys/cells.lib
+share/yosys/choices/
+share/yosys/choices/han-carlson.v
+share/yosys/choices/kogge-stone.v
+share/yosys/choices/sklansky.v
share/yosys/cmp2lcu.v
share/yosys/cmp2lut.v
+share/yosys/cmp2softlogic.v
share/yosys/coolrunner2/
share/yosys/coolrunner2/cells_counter_map.v
share/yosys/coolrunner2/cells_latch.v
@@ -31,14 +38,6 @@ share/yosys/coolrunner2/xc2_dff.lib
share/yosys/dff2ff.v
share/yosys/ecp5/
share/yosys/ecp5/arith_map.v
-share/yosys/ecp5/bram_conn_1.vh
-share/yosys/ecp5/bram_conn_18.vh
-share/yosys/ecp5/bram_conn_2.vh
-share/yosys/ecp5/bram_conn_36.vh
-share/yosys/ecp5/bram_conn_4.vh
-share/yosys/ecp5/bram_conn_9.vh
-share/yosys/ecp5/bram_init_1_2_4.vh
-share/yosys/ecp5/bram_init_9_18_36.vh
share/yosys/ecp5/brams.txt
share/yosys/ecp5/brams_map.v
share/yosys/ecp5/cells_bb.v
@@ -57,15 +56,40 @@ share/yosys/efinix/brams_map.v
share/yosys/efinix/cells_map.v
share/yosys/efinix/cells_sim.v
share/yosys/efinix/gbuf_map.v
+share/yosys/fabulous/
+share/yosys/fabulous/arith_map.v
+share/yosys/fabulous/cells_map.v
+share/yosys/fabulous/ff_map.v
+share/yosys/fabulous/io_map.v
+share/yosys/fabulous/latches_map.v
+share/yosys/fabulous/prims.v
+share/yosys/fabulous/ram_regfile.txt
+share/yosys/fabulous/regfile_map.v
share/yosys/gate2lut.v
+share/yosys/gatemate/
+share/yosys/gatemate/arith_map.v
+share/yosys/gatemate/brams.txt
+share/yosys/gatemate/brams_init_20.vh
+share/yosys/gatemate/brams_init_40.vh
+share/yosys/gatemate/brams_map.v
+share/yosys/gatemate/cells_bb.v
+share/yosys/gatemate/cells_sim.v
+share/yosys/gatemate/inv_map.v
+share/yosys/gatemate/lut_map.v
+share/yosys/gatemate/lut_tree_cells.genlib
+share/yosys/gatemate/lut_tree_map.v
+share/yosys/gatemate/mul_map.v
+share/yosys/gatemate/mux_map.v
+share/yosys/gatemate/reg_map.v
share/yosys/gowin/
share/yosys/gowin/arith_map.v
-share/yosys/gowin/bram_init_16.vh
share/yosys/gowin/brams.txt
-share/yosys/gowin/brams_init3.vh
share/yosys/gowin/brams_map.v
share/yosys/gowin/cells_map.v
share/yosys/gowin/cells_sim.v
+share/yosys/gowin/cells_xtra_gw1n.v
+share/yosys/gowin/cells_xtra_gw2a.v
+share/yosys/gowin/cells_xtra_gw5a.v
share/yosys/gowin/lutrams.txt
share/yosys/gowin/lutrams_map.v
share/yosys/greenpak4/
@@ -81,51 +105,75 @@ share/yosys/ice40/
share/yosys/ice40/abc9_model.v
share/yosys/ice40/arith_map.v
share/yosys/ice40/brams.txt
-share/yosys/ice40/brams_init1.vh
-share/yosys/ice40/brams_init2.vh
-share/yosys/ice40/brams_init3.vh
share/yosys/ice40/brams_map.v
share/yosys/ice40/cells_map.v
share/yosys/ice40/cells_sim.v
share/yosys/ice40/dsp_map.v
share/yosys/ice40/ff_map.v
share/yosys/ice40/latches_map.v
+share/yosys/ice40/spram.txt
+share/yosys/ice40/spram_map.v
share/yosys/include/
share/yosys/include/backends/
share/yosys/include/backends/cxxrtl/
-share/yosys/include/backends/cxxrtl/cxxrtl.h
-share/yosys/include/backends/cxxrtl/cxxrtl_capi.cc
-share/yosys/include/backends/cxxrtl/cxxrtl_capi.h
-share/yosys/include/backends/cxxrtl/cxxrtl_vcd.h
-share/yosys/include/backends/cxxrtl/cxxrtl_vcd_capi.cc
-share/yosys/include/backends/cxxrtl/cxxrtl_vcd_capi.h
+share/yosys/include/backends/cxxrtl/runtime/
+share/yosys/include/backends/cxxrtl/runtime/cxxrtl/
+share/yosys/include/backends/cxxrtl/runtime/cxxrtl/capi/
+share/yosys/include/backends/cxxrtl/runtime/cxxrtl/capi/cxxrtl_capi.cc
+share/yosys/include/backends/cxxrtl/runtime/cxxrtl/capi/cxxrtl_capi.h
+share/yosys/include/backends/cxxrtl/runtime/cxxrtl/capi/cxxrtl_capi_vcd.cc
+share/yosys/include/backends/cxxrtl/runtime/cxxrtl/capi/cxxrtl_capi_vcd.h
+share/yosys/include/backends/cxxrtl/runtime/cxxrtl/cxxrtl.h
+share/yosys/include/backends/cxxrtl/runtime/cxxrtl/cxxrtl_replay.h
+share/yosys/include/backends/cxxrtl/runtime/cxxrtl/cxxrtl_time.h
+share/yosys/include/backends/cxxrtl/runtime/cxxrtl/cxxrtl_vcd.h
share/yosys/include/backends/rtlil/
share/yosys/include/backends/rtlil/rtlil_backend.h
share/yosys/include/frontends/
share/yosys/include/frontends/ast/
share/yosys/include/frontends/ast/ast.h
+share/yosys/include/frontends/ast/ast_binding.h
+share/yosys/include/frontends/blif/
+share/yosys/include/frontends/blif/blifparse.h
share/yosys/include/kernel/
+share/yosys/include/kernel/binding.h
+share/yosys/include/kernel/bitpattern.h
+share/yosys/include/kernel/cellaigs.h
share/yosys/include/kernel/celledges.h
share/yosys/include/kernel/celltypes.h
share/yosys/include/kernel/consteval.h
share/yosys/include/kernel/constids.inc
+share/yosys/include/kernel/cost.h
+share/yosys/include/kernel/drivertools.h
share/yosys/include/kernel/ff.h
share/yosys/include/kernel/ffinit.h
+share/yosys/include/kernel/ffmerge.h
+share/yosys/include/kernel/fmt.h
+share/yosys/include/kernel/fstdata.h
share/yosys/include/kernel/hashlib.h
+share/yosys/include/kernel/json.h
share/yosys/include/kernel/log.h
share/yosys/include/kernel/macc.h
share/yosys/include/kernel/mem.h
share/yosys/include/kernel/modtools.h
+share/yosys/include/kernel/qcsat.h
share/yosys/include/kernel/register.h
share/yosys/include/kernel/rtlil.h
share/yosys/include/kernel/satgen.h
+share/yosys/include/kernel/scopeinfo.h
+share/yosys/include/kernel/sexpr.h
share/yosys/include/kernel/sigtools.h
+share/yosys/include/kernel/timinginfo.h
share/yosys/include/kernel/utils.h
share/yosys/include/kernel/yosys.h
+share/yosys/include/kernel/yosys_common.h
+share/yosys/include/kernel/yw.h
share/yosys/include/libs/
share/yosys/include/libs/ezsat/
share/yosys/include/libs/ezsat/ezminisat.h
share/yosys/include/libs/ezsat/ezsat.h
+share/yosys/include/libs/fst/
+share/yosys/include/libs/fst/fstapi.h
share/yosys/include/libs/json11/
share/yosys/include/libs/json11/json11.hpp
share/yosys/include/libs/sha1/
@@ -161,8 +209,7 @@ share/yosys/intel_alm/common/alm_map.v
share/yosys/intel_alm/common/alm_sim.v
share/yosys/intel_alm/common/arith_alm_map.v
share/yosys/intel_alm/common/bram_m10k.txt
-share/yosys/intel_alm/common/bram_m20k.txt
-share/yosys/intel_alm/common/bram_m20k_map.v
+share/yosys/intel_alm/common/bram_m10k_map.v
share/yosys/intel_alm/common/dff_map.v
share/yosys/intel_alm/common/dff_sim.v
share/yosys/intel_alm/common/dsp_map.v
@@ -171,17 +218,74 @@ share/yosys/intel_alm/common/lutram_mlab.txt
share/yosys/intel_alm/common/megafunction_bb.v
share/yosys/intel_alm/common/mem_sim.v
share/yosys/intel_alm/common/misc_sim.v
-share/yosys/intel_alm/common/quartus_rename.v
share/yosys/intel_alm/cyclonev/
share/yosys/intel_alm/cyclonev/cells_sim.v
-share/yosys/machxo2/
-share/yosys/machxo2/cells_map.v
-share/yosys/machxo2/cells_sim.v
+share/yosys/lattice/
+share/yosys/lattice/arith_map_ccu2c.v
+share/yosys/lattice/arith_map_ccu2d.v
+share/yosys/lattice/brams_16kd.txt
+share/yosys/lattice/brams_8kc.txt
+share/yosys/lattice/brams_map_16kd.v
+share/yosys/lattice/brams_map_8kc.v
+share/yosys/lattice/ccu2c_sim.vh
+share/yosys/lattice/ccu2d_sim.vh
+share/yosys/lattice/cells_bb_ecp5.v
+share/yosys/lattice/cells_bb_xo2.v
+share/yosys/lattice/cells_bb_xo3.v
+share/yosys/lattice/cells_bb_xo3d.v
+share/yosys/lattice/cells_ff.vh
+share/yosys/lattice/cells_io.vh
+share/yosys/lattice/cells_map.v
+share/yosys/lattice/cells_sim_ecp5.v
+share/yosys/lattice/cells_sim_xo2.v
+share/yosys/lattice/cells_sim_xo3.v
+share/yosys/lattice/cells_sim_xo3d.v
+share/yosys/lattice/common_sim.vh
+share/yosys/lattice/dsp_map_18x18.v
+share/yosys/lattice/latches_map.v
+share/yosys/lattice/lutrams.txt
+share/yosys/lattice/lutrams_map.v
+share/yosys/microchip/
+share/yosys/microchip/LSRAM.txt
+share/yosys/microchip/LSRAM_map.v
+share/yosys/microchip/arith_map.v
+share/yosys/microchip/brams_defs.vh
+share/yosys/microchip/cells_map.v
+share/yosys/microchip/cells_sim.v
+share/yosys/microchip/polarfire_dsp_map.v
+share/yosys/microchip/uSRAM.txt
+share/yosys/microchip/uSRAM_map.v
share/yosys/mul2dsp.v
+share/yosys/nanoxplore/
+share/yosys/nanoxplore/arith_map.v
+share/yosys/nanoxplore/brams.txt
+share/yosys/nanoxplore/brams_init.vh
+share/yosys/nanoxplore/brams_map.v
+share/yosys/nanoxplore/cells_bb.v
+share/yosys/nanoxplore/cells_bb_l.v
+share/yosys/nanoxplore/cells_bb_m.v
+share/yosys/nanoxplore/cells_bb_u.v
+share/yosys/nanoxplore/cells_map.v
+share/yosys/nanoxplore/cells_sim.v
+share/yosys/nanoxplore/cells_sim_l.v
+share/yosys/nanoxplore/cells_sim_m.v
+share/yosys/nanoxplore/cells_sim_u.v
+share/yosys/nanoxplore/cells_wrap.v
+share/yosys/nanoxplore/cells_wrap_l.v
+share/yosys/nanoxplore/cells_wrap_m.v
+share/yosys/nanoxplore/cells_wrap_u.v
+share/yosys/nanoxplore/io_map.v
+share/yosys/nanoxplore/latches_map.v
+share/yosys/nanoxplore/rf_init.vh
+share/yosys/nanoxplore/rf_rams_l.txt
+share/yosys/nanoxplore/rf_rams_m.txt
+share/yosys/nanoxplore/rf_rams_map_l.v
+share/yosys/nanoxplore/rf_rams_map_m.v
+share/yosys/nanoxplore/rf_rams_map_u.v
+share/yosys/nanoxplore/rf_rams_u.txt
share/yosys/nexus/
share/yosys/nexus/arith_map.v
share/yosys/nexus/brams.txt
-share/yosys/nexus/brams_init.vh
share/yosys/nexus/brams_map.v
share/yosys/nexus/cells_map.v
share/yosys/nexus/cells_sim.v
@@ -189,7 +293,6 @@ share/yosys/nexus/cells_xtra.v
share/yosys/nexus/dsp_map.v
share/yosys/nexus/latches_map.v
share/yosys/nexus/lrams.txt
-share/yosys/nexus/lrams_init.vh
share/yosys/nexus/lrams_map.v
share/yosys/nexus/lutrams.txt
share/yosys/nexus/lutrams_map.v
@@ -199,58 +302,77 @@ share/yosys/python3/
${MODPY_COMMENT}share/yosys/python3/${MODPY_PYCACHE}/
share/yosys/python3/${MODPY_PYCACHE}smtio.${MODPY_PYC_MAGIC_TAG}${MODPY_PYOEXTENSION}
share/yosys/python3/${MODPY_PYCACHE}smtio.${MODPY_PYC_MAGIC_TAG}pyc
+share/yosys/python3/${MODPY_PYCACHE}ywio.${MODPY_PYC_MAGIC_TAG}${MODPY_PYOEXTENSION}
+share/yosys/python3/${MODPY_PYCACHE}ywio.${MODPY_PYC_MAGIC_TAG}pyc
share/yosys/python3/smtio.py
+share/yosys/python3/ywio.py
share/yosys/quicklogic/
-share/yosys/quicklogic/abc9_map.v
-share/yosys/quicklogic/abc9_model.v
-share/yosys/quicklogic/abc9_unmap.v
-share/yosys/quicklogic/cells_sim.v
-share/yosys/quicklogic/lut_sim.v
-share/yosys/quicklogic/pp3_cells_map.v
-share/yosys/quicklogic/pp3_cells_sim.v
-share/yosys/quicklogic/pp3_ffs_map.v
-share/yosys/quicklogic/pp3_latches_map.v
-share/yosys/quicklogic/pp3_lut_map.v
+share/yosys/quicklogic/common/
+share/yosys/quicklogic/common/cells_sim.v
+share/yosys/quicklogic/pp3/
+share/yosys/quicklogic/pp3/abc9_map.v
+share/yosys/quicklogic/pp3/abc9_model.v
+share/yosys/quicklogic/pp3/abc9_unmap.v
+share/yosys/quicklogic/pp3/cells_map.v
+share/yosys/quicklogic/pp3/cells_sim.v
+share/yosys/quicklogic/pp3/ffs_map.v
+share/yosys/quicklogic/pp3/latches_map.v
+share/yosys/quicklogic/pp3/lut_map.v
+share/yosys/quicklogic/qlf_k6n10f/
+share/yosys/quicklogic/qlf_k6n10f/TDP18K_FIFO.v
+share/yosys/quicklogic/qlf_k6n10f/arith_map.v
+share/yosys/quicklogic/qlf_k6n10f/bram_types_sim.v
+share/yosys/quicklogic/qlf_k6n10f/brams_map.v
+share/yosys/quicklogic/qlf_k6n10f/brams_sim.v
+share/yosys/quicklogic/qlf_k6n10f/cells_sim.v
+share/yosys/quicklogic/qlf_k6n10f/dsp_final_map.v
+share/yosys/quicklogic/qlf_k6n10f/dsp_map.v
+share/yosys/quicklogic/qlf_k6n10f/dsp_sim.v
+share/yosys/quicklogic/qlf_k6n10f/ffs_map.v
+share/yosys/quicklogic/qlf_k6n10f/libmap_brams.txt
+share/yosys/quicklogic/qlf_k6n10f/libmap_brams_map.v
+share/yosys/quicklogic/qlf_k6n10f/sram1024x18_mem.v
+share/yosys/quicklogic/qlf_k6n10f/ufifo_ctl.v
share/yosys/sf2/
share/yosys/sf2/arith_map.v
share/yosys/sf2/cells_map.v
share/yosys/sf2/cells_sim.v
share/yosys/simcells.v
share/yosys/simlib.v
+share/yosys/smtmap.v
share/yosys/techmap.v
share/yosys/xilinx/
share/yosys/xilinx/abc9_model.v
share/yosys/xilinx/arith_map.v
-share/yosys/xilinx/brams_init_16.vh
-share/yosys/xilinx/brams_init_18.vh
-share/yosys/xilinx/brams_init_32.vh
-share/yosys/xilinx/brams_init_36.vh
-share/yosys/xilinx/brams_init_8.vh
-share/yosys/xilinx/brams_init_9.vh
+share/yosys/xilinx/brams_defs.vh
+share/yosys/xilinx/brams_xc2v.txt
+share/yosys/xilinx/brams_xc2v_map.v
+share/yosys/xilinx/brams_xc3sda.txt
+share/yosys/xilinx/brams_xc3sda_map.v
+share/yosys/xilinx/brams_xc4v.txt
+share/yosys/xilinx/brams_xc4v_map.v
+share/yosys/xilinx/brams_xc5v_map.v
+share/yosys/xilinx/brams_xc6v_map.v
+share/yosys/xilinx/brams_xcu_map.v
+share/yosys/xilinx/brams_xcv.txt
+share/yosys/xilinx/brams_xcv_map.v
share/yosys/xilinx/cells_map.v
share/yosys/xilinx/cells_sim.v
share/yosys/xilinx/cells_xtra.v
share/yosys/xilinx/ff_map.v
-share/yosys/xilinx/lut4_lutrams.txt
-share/yosys/xilinx/lut6_lutrams.txt
share/yosys/xilinx/lut_map.v
-share/yosys/xilinx/lutrams_map.v
+share/yosys/xilinx/lutrams_xc5v.txt
+share/yosys/xilinx/lutrams_xc5v_map.v
+share/yosys/xilinx/lutrams_xcu.txt
+share/yosys/xilinx/lutrams_xcv.txt
+share/yosys/xilinx/lutrams_xcv_map.v
share/yosys/xilinx/mux_map.v
-share/yosys/xilinx/xc2v_brams.txt
-share/yosys/xilinx/xc2v_brams_map.v
+share/yosys/xilinx/urams.txt
+share/yosys/xilinx/urams_map.v
share/yosys/xilinx/xc3s_mult_map.v
-share/yosys/xilinx/xc3sa_brams.txt
-share/yosys/xilinx/xc3sda_brams.txt
share/yosys/xilinx/xc3sda_dsp_map.v
share/yosys/xilinx/xc4v_dsp_map.v
share/yosys/xilinx/xc5v_dsp_map.v
-share/yosys/xilinx/xc6s_brams.txt
-share/yosys/xilinx/xc6s_brams_map.v
share/yosys/xilinx/xc6s_dsp_map.v
-share/yosys/xilinx/xc7_brams_map.v
share/yosys/xilinx/xc7_dsp_map.v
-share/yosys/xilinx/xc7_xcu_brams.txt
-share/yosys/xilinx/xcu_brams_map.v
share/yosys/xilinx/xcu_dsp_map.v
-share/yosys/xilinx/xcup_urams.txt
-share/yosys/xilinx/xcup_urams_map.v
