On 2021/05/23 13:06, Alessandro De Laurenzis wrote:
> Greetings,
>
> The attached diff updates cad/yosys to a very recent commit.
>
> This is the first update of this port since its addition to the tree; I was
> initially skeptical to jump away from the most recent tags (published in
> 2019...), but as matter of facts this project is very actively developed and
> more than 5000 commits have been made since then.
>
> Simply, upstream is using an "internal" version tracking that is recorded
> into a variable in their Makefile.
+ isn't really supported in ports infrastructure (it is accepted and
allows packaging, but will mean that updates are compared alphabetically
rather than numerically). "pl" is right for this use:
$ pkg_check-version yosys-0.9+4081 yosys-0.9+10000
yosys-*- sorted: yosys-0.9+10000 yosys-0.9+4081
$ pkg_check-version yosys-0.9pl4081 yosys-0.9pl10000
yosys-*- sorted: yosys-0.9pl4081 yosys-0.9pl10000
> - change COMPILER from "base-clang ports-gcc" to "base-clang ports-clang" to
> make the subsequent "make config-clang" in do-configure more consistent
> through all archs;
I think this should be dropped. ports-clang is normally only used
where it's required; really if an arch is ready to move to using clang
by default then it would be moved in base as well. Looking at what it
actually does in the Makefile, the only difference is setting some
things up for sanitizer builds, this doesn't work on OpenBSD anyway.
(It sets defaults for CXX/LD but we override them in the port anyway).
How about this diff?
Index: Makefile
===================================================================
RCS file: /cvs/ports/cad/yosys/Makefile,v
retrieving revision 1.11
diff -u -p -r1.11 Makefile
--- Makefile 23 Feb 2021 19:39:10 -0000 1.11
+++ Makefile 23 May 2021 12:58:09 -0000
@@ -1,12 +1,11 @@
# $OpenBSD: Makefile,v 1.11 2021/02/23 19:39:10 sthen Exp $
COMMENT = framework for Verilog RTL synthesis
+DISTNAME = yosys-0.9pl4081
GH_ACCOUNT = YosysHQ
GH_PROJECT = yosys
-GH_TAGNAME = yosys-0.9
-DISTNAME = ${GH_TAGNAME}
-REVISION = 1
+GH_COMMIT = 25de8faf10157ab0cb40f77c7cbf3143527c598e
CATEGORIES = cad
@@ -14,15 +13,16 @@ HOMEPAGE = http://www.clifford.at/yosys/
MAINTAINER = Alessandro De Laurenzis <[email protected]>
# ISC (yosys), MIT (MiniSat)
-PERMIT_PACKAGE = Yes
+PERMIT_PACKAGE = Yes
-WANTLIB += ${COMPILER_LIBCXX} ${MODTCL_WANTLIB} c m readline ffi
+WANTLIB += ${COMPILER_LIBCXX} ${MODTCL_WANTLIB} c m readline ffi z
# C++11
COMPILER = base-clang ports-gcc
MODULES = lang/python \
lang/tcl
+
CONFIGURE_STYLE = none
BUILD_DEPENDS = devel/bison \
@@ -56,6 +56,8 @@ TEST_ENV = MAKE="${MAKE_PROGRAM}"
FAKE_FLAGS = PREFIX="${TRUEPREFIX}"
+# the only gcc-specific things from "config-gcc" are setting CXX/LD, which
+# we override above
do-configure:
@${SUBST_CMD} ${WRKSRC}/kernel/yosys.cc
@cd ${WRKBUILD} && exec env -i ${MAKE_ENV} ${MAKE_PROGRAM} config-gcc
Index: distinfo
===================================================================
RCS file: /cvs/ports/cad/yosys/distinfo,v
retrieving revision 1.3
diff -u -p -r1.3 distinfo
--- distinfo 28 Oct 2019 08:00:17 -0000 1.3
+++ distinfo 23 May 2021 12:58:09 -0000
@@ -1,2 +1,2 @@
-SHA256 (yosys-0.9.tar.gz) = 8uMTcfnPGzbLT1eyP9brhJrcfZNdz0nzyQWqUTY4LC8=
-SIZE (yosys-0.9.tar.gz) = 1299545
+SHA256 (yosys-0.9pl4081-25de8faf.tar.gz) =
ProWZDm6xHgXlv8M1zJn+b4zrgGUIUpap6YV5MrdKRM=
+SIZE (yosys-0.9pl4081-25de8faf.tar.gz) = 1976189
Index: patches/patch-Makefile
===================================================================
RCS file: /cvs/ports/cad/yosys/patches/patch-Makefile,v
retrieving revision 1.2
diff -u -p -r1.2 patch-Makefile
--- patches/patch-Makefile 9 Jan 2019 04:27:10 -0000 1.2
+++ patches/patch-Makefile 23 May 2021 12:58:09 -0000
@@ -3,49 +3,32 @@ $OpenBSD: patch-Makefile,v 1.2 2019/01/0
Index: Makefile
--- Makefile.orig
+++ Makefile
-@@ -63,7 +63,7 @@ all: top-all
+@@ -85,7 +85,7 @@ all: top-all
YOSYS_SRC := $(dir $(firstword $(MAKEFILE_LIST)))
VPATH := $(YOSYS_SRC)
--CXXFLAGS := $(CXXFLAGS) -Wall -Wextra -ggdb -I. -I"$(YOSYS_SRC)" -MD
-D_YOSYS_ -fPIC -I$(PREFIX)/include
-+CXXFLAGS := $(CXXFLAGS) -Wall -Wextra -I. -I"$(YOSYS_SRC)" -MD -D_YOSYS_
-fPIC -I$(PREFIX)/include
- LDFLAGS := $(LDFLAGS) -L$(LIBDIR)
+-CXXFLAGS := $(CXXFLAGS) -Wall -Wextra -ggdb -I. -I"$(YOSYS_SRC)" -MD -MP
-D_YOSYS_ -fPIC -I$(PREFIX)/include
++CXXFLAGS := $(CXXFLAGS) -Wall -Wextra -I. -I"$(YOSYS_SRC)" -MD -MP -D_YOSYS_
-fPIC -I$(PREFIX)/include
LDLIBS := $(LDLIBS) -lstdc++ -lm
PLUGIN_LDFLAGS :=
-@@ -94,6 +94,8 @@ PKG_CONFIG_PATH := $(PORT_PREFIX)/lib/pkgconfig:$(PKG_
- export PATH := $(PORT_PREFIX)/bin:$(PATH)
+
+@@ -349,6 +349,10 @@ else ifneq ($(CONFIG),none)
+ $(error Invalid CONFIG setting '$(CONFIG)'. Valid values: clang, gcc,
gcc-4.8, emcc, mxe, msys2-32, msys2-64)
endif
-+else ifeq ($(OS), OpenBSD)
++ifeq ($(OS), OpenBSD)
++LDLIBS := $(filter-out -lrt, $(LDLIBS))
++endif
+
- else
- LDFLAGS += -rdynamic
- LDLIBS += -lrt
-@@ -131,7 +133,7 @@ endif
- ifeq ($(CONFIG),clang)
- CXX = clang
- LD = clang++
--CXXFLAGS += -std=c++11 -Os
-+CXXFLAGS += -std=c++11
- ABCMKARGS += ARCHFLAGS="-DABC_USE_STDINT_H"
-
- ifneq ($(SANITIZER),)
-@@ -154,7 +156,7 @@ endif
- else ifeq ($(CONFIG),gcc)
- CXX = gcc
- LD = gcc
--CXXFLAGS += -std=c++11 -Os
-+CXXFLAGS += -std=c++11
- ABCMKARGS += ARCHFLAGS="-DABC_USE_STDINT_H"
-
- else ifeq ($(CONFIG),gcc-static)
-@@ -293,7 +295,9 @@ ifeq ($(ENABLE_PLUGINS),1)
+ ifeq ($(ENABLE_LIBYOSYS),1)
+ TARGETS += libyosys.so
+ endif
+@@ -439,7 +443,7 @@ endif
+ ifeq ($(ENABLE_PLUGINS),1)
CXXFLAGS += $(shell PKG_CONFIG_PATH=$(PKG_CONFIG_PATH) $(PKG_CONFIG)
--silence-errors --cflags libffi) -DYOSYS_ENABLE_PLUGINS
LDLIBS += $(shell PKG_CONFIG_PATH=$(PKG_CONFIG_PATH) $(PKG_CONFIG)
--silence-errors --libs libffi || echo -lffi)
- ifneq ($(OS), FreeBSD)
-+ifneq ($(OS), OpenBSD)
+-ifneq ($(OS), FreeBSD)
++ifneq ($(OS), $(filter $(OS), FreeBSD OpenBSD))
LDLIBS += -ldl
-+endif
endif
endif
-
Index: patches/patch-kernel_yosys_cc
===================================================================
RCS file: /cvs/ports/cad/yosys/patches/patch-kernel_yosys_cc,v
retrieving revision 1.2
diff -u -p -r1.2 patch-kernel_yosys_cc
--- patches/patch-kernel_yosys_cc 9 Jan 2019 04:27:10 -0000 1.2
+++ patches/patch-kernel_yosys_cc 23 May 2021 12:58:09 -0000
@@ -3,8 +3,8 @@ $OpenBSD: patch-kernel_yosys_cc,v 1.2 20
Index: kernel/yosys.cc
--- kernel/yosys.cc.orig
+++ kernel/yosys.cc
-@@ -55,6 +55,10 @@
- # include <sys/sysctl.h>
+@@ -69,6 +69,10 @@
+ #endif
#endif
+#ifdef __OpenBSD__
@@ -14,9 +14,9 @@ Index: kernel/yosys.cc
#include <limits.h>
#include <errno.h>
-@@ -726,6 +730,11 @@ std::string proc_self_dirname()
- for (i = 0; shortpath[i]; i++)
- path += char(shortpath[i]);
+@@ -787,6 +791,11 @@ std::string proc_self_dirname()
+ path.assign(buffer, buflen);
+ free(buffer);
return path;
+}
+#elif defined(__OpenBSD__)
@@ -24,5 +24,5 @@ Index: kernel/yosys.cc
+{
+ return "${PREFIX}/bin/";
}
- #elif defined(EMSCRIPTEN)
+ #elif defined(__APPLE__)
std::string proc_self_dirname()
Index: patches/patch-passes_cmds_show_cc
===================================================================
RCS file: /cvs/ports/cad/yosys/patches/patch-passes_cmds_show_cc,v
retrieving revision 1.1
diff -u -p -r1.1 patch-passes_cmds_show_cc
--- patches/patch-passes_cmds_show_cc 30 Apr 2019 07:21:58 -0000 1.1
+++ patches/patch-passes_cmds_show_cc 23 May 2021 12:58:09 -0000
@@ -3,12 +3,12 @@ $OpenBSD: patch-passes_cmds_show_cc,v 1.
Index: passes/cmds/show.cc
--- passes/cmds/show.cc.orig
+++ passes/cmds/show.cc
-@@ -847,7 +847,7 @@ struct ShowPass : public Pass {
- log_cmd_error("Shell command failed!\n");
- } else
- if (format.empty()) {
-- std::string cmd = stringf("{ test -f '%s.pid' && fuser
-s '%s.pid'; } || ( echo $$ >&3; exec xdot '%s'; ) 3> '%s.pid' &",
dot_file.c_str(), dot_file.c_str(), dot_file.c_str(), dot_file.c_str());
-+ std::string cmd = stringf("test -f '%s.pid' -a -n
\"`fuser '%s.pid' 2>/dev/null`\" || ( echo $$ >&3; exec xdot '%s'; ) 3>
'%s.pid' &", dot_file.c_str(), dot_file.c_str(), dot_file.c_str(),
dot_file.c_str());
+@@ -880,7 +880,7 @@ struct ShowPass : public Pass {
+ #ifdef __APPLE__
+ std::string cmd = stringf("ps -fu %d | grep -q '[ ]%s'
|| xdot '%s' %s", getuid(), dot_file.c_str(), dot_file.c_str(),
background.c_str());
+ #else
+- std::string cmd = stringf("{ test -f '%s.pid' && fuser
-s '%s.pid' 2> /dev/null; } || ( echo $$ >&3; exec xdot '%s'; ) 3> '%s.pid'
%s", dot_file.c_str(), dot_file.c_str(), dot_file.c_str(), dot_file.c_str(),
background.c_str());
++ std::string cmd = stringf("test -f '%s.pid' -a -n
\"`fuser '%s.pid' 2>/dev/null`\" || ( echo $$ >&3; exec xdot '%s'; ) 3>
'%s.pid' %s", dot_file.c_str(), dot_file.c_str(), dot_file.c_str(),
dot_file.c_str(), background.c_str());
+ #endif
log("Exec: %s\n", cmd.c_str());
if (run_command(cmd) != 0)
- log_cmd_error("Shell command failed!\n");
Index: pkg/PLIST
===================================================================
RCS file: /cvs/ports/cad/yosys/pkg/PLIST,v
retrieving revision 1.3
diff -u -p -r1.3 PLIST
--- pkg/PLIST 28 Oct 2019 08:00:17 -0000 1.3
+++ pkg/PLIST 23 May 2021 12:58:09 -0000
@@ -4,6 +4,9 @@ bin/yosys-config
@bin bin/yosys-filterlib
bin/yosys-smtbmc
share/yosys/
+share/yosys/abc9_map.v
+share/yosys/abc9_model.v
+share/yosys/abc9_unmap.v
share/yosys/achronix/
share/yosys/achronix/speedster22i/
share/yosys/achronix/speedster22i/cells_map.v
@@ -13,13 +16,15 @@ share/yosys/anlogic/
share/yosys/anlogic/arith_map.v
share/yosys/anlogic/cells_map.v
share/yosys/anlogic/cells_sim.v
-share/yosys/anlogic/dram_init_16x4.vh
-share/yosys/anlogic/drams.txt
-share/yosys/anlogic/drams_map.v
share/yosys/anlogic/eagle_bb.v
+share/yosys/anlogic/lutram_init_16x4.vh
+share/yosys/anlogic/lutrams.txt
+share/yosys/anlogic/lutrams_map.v
share/yosys/cells.lib
+share/yosys/cmp2lcu.v
share/yosys/cmp2lut.v
share/yosys/coolrunner2/
+share/yosys/coolrunner2/cells_counter_map.v
share/yosys/coolrunner2/cells_latch.v
share/yosys/coolrunner2/cells_sim.v
share/yosys/coolrunner2/tff_extract.v
@@ -27,31 +32,43 @@ share/yosys/coolrunner2/xc2_dff.lib
share/yosys/dff2ff.v
share/yosys/ecp5/
share/yosys/ecp5/arith_map.v
-share/yosys/ecp5/bram.txt
share/yosys/ecp5/bram_conn_1.vh
share/yosys/ecp5/bram_conn_18.vh
share/yosys/ecp5/bram_conn_2.vh
+share/yosys/ecp5/bram_conn_36.vh
share/yosys/ecp5/bram_conn_4.vh
share/yosys/ecp5/bram_conn_9.vh
share/yosys/ecp5/bram_init_1_2_4.vh
share/yosys/ecp5/bram_init_9_18_36.vh
+share/yosys/ecp5/brams.txt
share/yosys/ecp5/brams_map.v
share/yosys/ecp5/cells_bb.v
+share/yosys/ecp5/cells_ff.vh
+share/yosys/ecp5/cells_io.vh
share/yosys/ecp5/cells_map.v
share/yosys/ecp5/cells_sim.v
-share/yosys/ecp5/dram.txt
-share/yosys/ecp5/drams_map.v
+share/yosys/ecp5/dsp_map.v
share/yosys/ecp5/latches_map.v
+share/yosys/ecp5/lutrams.txt
+share/yosys/ecp5/lutrams_map.v
+share/yosys/efinix/
+share/yosys/efinix/arith_map.v
+share/yosys/efinix/brams.txt
+share/yosys/efinix/brams_map.v
+share/yosys/efinix/cells_map.v
+share/yosys/efinix/cells_sim.v
+share/yosys/efinix/gbuf_map.v
share/yosys/gate2lut.v
share/yosys/gowin/
share/yosys/gowin/arith_map.v
-share/yosys/gowin/bram.txt
+share/yosys/gowin/bram_init_16.vh
+share/yosys/gowin/brams.txt
share/yosys/gowin/brams_init3.vh
share/yosys/gowin/brams_map.v
share/yosys/gowin/cells_map.v
share/yosys/gowin/cells_sim.v
-share/yosys/gowin/dram.txt
-share/yosys/gowin/drams_map.v
+share/yosys/gowin/lutrams.txt
+share/yosys/gowin/lutrams_map.v
share/yosys/greenpak4/
share/yosys/greenpak4/cells_blackbox.v
share/yosys/greenpak4/cells_latch.v
@@ -62,6 +79,7 @@ share/yosys/greenpak4/cells_sim_digital.
share/yosys/greenpak4/cells_sim_wip.v
share/yosys/greenpak4/gp_dff.lib
share/yosys/ice40/
+share/yosys/ice40/abc9_model.v
share/yosys/ice40/arith_map.v
share/yosys/ice40/brams.txt
share/yosys/ice40/brams_init1.vh
@@ -70,11 +88,20 @@ share/yosys/ice40/brams_init3.vh
share/yosys/ice40/brams_map.v
share/yosys/ice40/cells_map.v
share/yosys/ice40/cells_sim.v
+share/yosys/ice40/dsp_map.v
+share/yosys/ice40/ff_map.v
share/yosys/ice40/latches_map.v
share/yosys/include/
share/yosys/include/backends/
-share/yosys/include/backends/ilang/
-share/yosys/include/backends/ilang/ilang_backend.h
+share/yosys/include/backends/cxxrtl/
+share/yosys/include/backends/cxxrtl/cxxrtl.h
+share/yosys/include/backends/cxxrtl/cxxrtl_capi.cc
+share/yosys/include/backends/cxxrtl/cxxrtl_capi.h
+share/yosys/include/backends/cxxrtl/cxxrtl_vcd.h
+share/yosys/include/backends/cxxrtl/cxxrtl_vcd_capi.cc
+share/yosys/include/backends/cxxrtl/cxxrtl_vcd_capi.h
+share/yosys/include/backends/rtlil/
+share/yosys/include/backends/rtlil/rtlil_backend.h
share/yosys/include/frontends/
share/yosys/include/frontends/ast/
share/yosys/include/frontends/ast/ast.h
@@ -82,9 +109,13 @@ share/yosys/include/kernel/
share/yosys/include/kernel/celledges.h
share/yosys/include/kernel/celltypes.h
share/yosys/include/kernel/consteval.h
+share/yosys/include/kernel/constids.inc
+share/yosys/include/kernel/ff.h
+share/yosys/include/kernel/ffinit.h
share/yosys/include/kernel/hashlib.h
share/yosys/include/kernel/log.h
share/yosys/include/kernel/macc.h
+share/yosys/include/kernel/mem.h
share/yosys/include/kernel/modtools.h
share/yosys/include/kernel/register.h
share/yosys/include/kernel/rtlil.h
@@ -96,40 +127,90 @@ share/yosys/include/libs/
share/yosys/include/libs/ezsat/
share/yosys/include/libs/ezsat/ezminisat.h
share/yosys/include/libs/ezsat/ezsat.h
+share/yosys/include/libs/json11/
+share/yosys/include/libs/json11/json11.hpp
share/yosys/include/libs/sha1/
share/yosys/include/libs/sha1/sha1.h
share/yosys/include/passes/
share/yosys/include/passes/fsm/
share/yosys/include/passes/fsm/fsmdata.h
share/yosys/intel/
-share/yosys/intel/a10gx/
-share/yosys/intel/a10gx/cells_map.v
-share/yosys/intel/a10gx/cells_sim.v
share/yosys/intel/common/
share/yosys/intel/common/altpll_bb.v
-share/yosys/intel/common/brams.txt
-share/yosys/intel/common/brams_map.v
+share/yosys/intel/common/brams_m9k.txt
+share/yosys/intel/common/brams_map_m9k.v
+share/yosys/intel/common/ff_map.v
share/yosys/intel/common/m9k_bb.v
-share/yosys/intel/cyclone10/
-share/yosys/intel/cyclone10/cells_map.v
-share/yosys/intel/cyclone10/cells_sim.v
+share/yosys/intel/cyclone10lp/
+share/yosys/intel/cyclone10lp/cells_map.v
+share/yosys/intel/cyclone10lp/cells_sim.v
share/yosys/intel/cycloneiv/
share/yosys/intel/cycloneiv/cells_map.v
share/yosys/intel/cycloneiv/cells_sim.v
share/yosys/intel/cycloneive/
share/yosys/intel/cycloneive/cells_map.v
share/yosys/intel/cycloneive/cells_sim.v
-share/yosys/intel/cyclonev/
-share/yosys/intel/cyclonev/cells_map.v
-share/yosys/intel/cyclonev/cells_sim.v
share/yosys/intel/max10/
share/yosys/intel/max10/cells_map.v
share/yosys/intel/max10/cells_sim.v
+share/yosys/intel_alm/
+share/yosys/intel_alm/common/
+share/yosys/intel_alm/common/abc9_map.v
+share/yosys/intel_alm/common/abc9_model.v
+share/yosys/intel_alm/common/abc9_unmap.v
+share/yosys/intel_alm/common/alm_map.v
+share/yosys/intel_alm/common/alm_sim.v
+share/yosys/intel_alm/common/arith_alm_map.v
+share/yosys/intel_alm/common/bram_m10k.txt
+share/yosys/intel_alm/common/bram_m20k.txt
+share/yosys/intel_alm/common/bram_m20k_map.v
+share/yosys/intel_alm/common/dff_map.v
+share/yosys/intel_alm/common/dff_sim.v
+share/yosys/intel_alm/common/dsp_map.v
+share/yosys/intel_alm/common/dsp_sim.v
+share/yosys/intel_alm/common/lutram_mlab.txt
+share/yosys/intel_alm/common/megafunction_bb.v
+share/yosys/intel_alm/common/mem_sim.v
+share/yosys/intel_alm/common/misc_sim.v
+share/yosys/intel_alm/common/quartus_rename.v
+share/yosys/intel_alm/cyclonev/
+share/yosys/intel_alm/cyclonev/cells_sim.v
+share/yosys/machxo2/
+share/yosys/machxo2/cells_map.v
+share/yosys/machxo2/cells_sim.v
+share/yosys/mul2dsp.v
+share/yosys/nexus/
+share/yosys/nexus/arith_map.v
+share/yosys/nexus/brams.txt
+share/yosys/nexus/brams_init.vh
+share/yosys/nexus/brams_map.v
+share/yosys/nexus/cells_map.v
+share/yosys/nexus/cells_sim.v
+share/yosys/nexus/cells_xtra.v
+share/yosys/nexus/dsp_map.v
+share/yosys/nexus/latches_map.v
+share/yosys/nexus/lrams.txt
+share/yosys/nexus/lrams_init.vh
+share/yosys/nexus/lrams_map.v
+share/yosys/nexus/lutrams.txt
+share/yosys/nexus/lutrams_map.v
+share/yosys/nexus/parse_init.vh
share/yosys/pmux2mux.v
share/yosys/python3/
${MODPY_COMMENT}share/yosys/python3/${MODPY_PYCACHE}/
share/yosys/python3/${MODPY_PYCACHE}smtio.${MODPY_PYC_MAGIC_TAG}pyc
share/yosys/python3/smtio.py
+share/yosys/quicklogic/
+share/yosys/quicklogic/abc9_map.v
+share/yosys/quicklogic/abc9_model.v
+share/yosys/quicklogic/abc9_unmap.v
+share/yosys/quicklogic/cells_sim.v
+share/yosys/quicklogic/lut_sim.v
+share/yosys/quicklogic/pp3_cells_map.v
+share/yosys/quicklogic/pp3_cells_sim.v
+share/yosys/quicklogic/pp3_ffs_map.v
+share/yosys/quicklogic/pp3_latches_map.v
+share/yosys/quicklogic/pp3_lut_map.v
share/yosys/sf2/
share/yosys/sf2/arith_map.v
share/yosys/sf2/cells_map.v
@@ -138,18 +219,38 @@ share/yosys/simcells.v
share/yosys/simlib.v
share/yosys/techmap.v
share/yosys/xilinx/
+share/yosys/xilinx/abc9_model.v
share/yosys/xilinx/arith_map.v
-share/yosys/xilinx/brams.txt
-share/yosys/xilinx/brams_bb.v
share/yosys/xilinx/brams_init_16.vh
share/yosys/xilinx/brams_init_18.vh
share/yosys/xilinx/brams_init_32.vh
share/yosys/xilinx/brams_init_36.vh
-share/yosys/xilinx/brams_map.v
+share/yosys/xilinx/brams_init_8.vh
+share/yosys/xilinx/brams_init_9.vh
share/yosys/xilinx/cells_map.v
share/yosys/xilinx/cells_sim.v
share/yosys/xilinx/cells_xtra.v
-share/yosys/xilinx/drams.txt
-share/yosys/xilinx/drams_map.v
share/yosys/xilinx/ff_map.v
+share/yosys/xilinx/lut4_lutrams.txt
+share/yosys/xilinx/lut6_lutrams.txt
share/yosys/xilinx/lut_map.v
+share/yosys/xilinx/lutrams_map.v
+share/yosys/xilinx/mux_map.v
+share/yosys/xilinx/xc2v_brams.txt
+share/yosys/xilinx/xc2v_brams_map.v
+share/yosys/xilinx/xc3s_mult_map.v
+share/yosys/xilinx/xc3sa_brams.txt
+share/yosys/xilinx/xc3sda_brams.txt
+share/yosys/xilinx/xc3sda_dsp_map.v
+share/yosys/xilinx/xc4v_dsp_map.v
+share/yosys/xilinx/xc5v_dsp_map.v
+share/yosys/xilinx/xc6s_brams.txt
+share/yosys/xilinx/xc6s_brams_map.v
+share/yosys/xilinx/xc6s_dsp_map.v
+share/yosys/xilinx/xc7_brams_map.v
+share/yosys/xilinx/xc7_dsp_map.v
+share/yosys/xilinx/xc7_xcu_brams.txt
+share/yosys/xilinx/xcu_brams_map.v
+share/yosys/xilinx/xcu_dsp_map.v
+share/yosys/xilinx/xcup_urams.txt
+share/yosys/xilinx/xcup_urams_map.v
