Hi,
Abhishek Bhattacharjee wrote:
Hi all-
I had a question on how the backend hash maintaining the translation table
entries
> is allocated in Solaris. Is this data structure maintained in unmapped,
cacheable
memory? Or is the hash itself paged by the VM system? Any info on this would be
highly appreciated.
Are you asking how we avoid further TLB misses during the handling of a TLB
miss?
During TLB miss handling all data accesses are performed using physical
addresses. On sparc a TLB miss goes first to a software-maintained cache
called the TSB, and we use physical accesses for that; if that misses then
we must visit the hash, and we walk the hashbucket using physical
pointers; on sparc not using hardware miss handlers the code
we execute is in the locked-down "nucleus" large page of
kernel text, so we can't miss on instruction fetch either.
On x86 the CR3 register has a physical address of the
page directory in use, which has a physical address of a page
table etc etc and it's a hardware walk.
Gavin
_______________________________________________
opensolaris-code mailing list
[email protected]
http://mail.opensolaris.org/mailman/listinfo/opensolaris-code
