Gavin Maltby wrote: > When a virtual address is presented to the mmu it looks it up in the > TLBs (there are several, handling different page sizes). If it hits > it returns the translated physical address, otherwise we miss and > trap.
Technically, most recent CPUs contain both level-1 TLBs (instruction and data) as well as a larger (usually shared) second-level TLB and support for hardware table (TSB) walking. In such a CPU: - If you hit in the L1TLB (I or D) then the mapping is used. - If not, the hardware accesses the L2TLB itself and updates the L1TLB if it matches. - If not, and "table walk" is enabled, the hardware searches the TSB in memory (if in a compatible format) and installs the mapping if it is found. This is the "if you can see a valid entry in the TSB then you can use it" rule Gavin mentions. - Finally you get a trap if this fails and the OS takes over. Older CPUs went straight from "miss in L1TLB" to "OS trap", but this is not so good for performance. Hugh. _______________________________________________ opensolaris-code mailing list [email protected] http://mail.opensolaris.org/mailman/listinfo/opensolaris-code
