Dear OpenOCD dev community, I'm the maintainer of fpgacapzero (or fcapz) https://github.com/lcapossio/fpgacapZero/ an open-source cross-vendor FPGA JTAG debug cores, including logic analyzer (ELA), embedded I/O (EIO), JTAG to AXI bridge, etc.
I have AMD/Xilinx hw_server backend working and have implemented OpenOCD basic functionality but I'm not able to test it. I'm looking for help in an honest assessment of my openOCD backend and what are the best practices. Also if you can help with testing different cables it'd be really good too. Any help is appreciated and hopefully it will be of use to everyone. Cheers, Leo
