This is an automated email from Gerrit. "Name of user not set <[email protected]>" just uploaded a new patch set to Gerrit, which you can find at https://review.openocd.org/c/openocd/+/9523
-- gerrit commit c63d8abf59a0ca9cfa24cedf0bc241caaf651856 Author: Frederic Boyer <[email protected]> Date: Thu Apr 9 16:28:32 2026 +0200 tcl: add SAMA7G5 target and SAMA7G54-EK board configuration Add target configuration for the Microchip SAMA7G5 series (Cortex-A7 based MPU). Supports both JTAG and SWD interfaces. Add board configuration for the SAMA7G54-EK evaluation kit. Link: https://www.microchip.com/en-us/product/sama7g54 Link: https://www.microchip.com/en-us/development-tool/EV21H18A Change-Id: Ieda7658167e87c6f011b4c267d2598b80754e067 Signed-off-by: Frederic Boyer <[email protected]> diff --git a/tcl/board/microchip/sama7g54_ek.cfg b/tcl/board/microchip/sama7g54_ek.cfg new file mode 100644 index 0000000000..7e9f03a167 --- /dev/null +++ b/tcl/board/microchip/sama7g54_ek.cfg @@ -0,0 +1,76 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# +# Board configuration for Microchip SAMA7G54-EK evaluation kit +# https://www.microchip.com/en-us/development-tool/EV21H18A +# Datasheet: DS60001765 +# User Guide: DS50003273 +# +# Debug Interface Selection: +# The SAMA7G54-EK has TWO debug paths controlled by jumper J26: +# +# J26 OPEN (factory default): +# - On-board J-Link-OB (ATSAM3U4C) is ENABLED +# - Connect via USB port J24 +# - Provides JTAG + CDC serial (virtual COM port) +# +# J26 CLOSED (this board file's default configuration): +# - On-board J-Link-OB is DISABLED +# - External JTAG/SWD probe connects to 20-pin header J27 +# +# IMPORTANT: J27 is only active when J26 is CLOSED. +# Using J27 with J26 open will NOT work. +# +# IMPORTANT: +# First-time JTAG Connection on blank board (no AT91Bootstrap in NVM): +# 1. Power on the board via J7 (USB Micro-AB) or J1 (DC jack) +# 2. ROM code searches for valid boot media +# 3. No valid code found -> ROM enters SAM-BA Monitor +# 4. SAM-BA Monitor enables JTAG -- OpenOCD can now connect +# To force SAM-BA entry on a board with programmed NVM: +# - Press and hold SW4 (DISABLE_BOOT) during power-on, OR +# - Close jumper J22 to permanently disable on-board boot memories +# - LED D8 RED = boot memories disabled, GREEN = enabled +# - Note: SW4/J22 does NOT disable SD Card boot -- remove card from J4 +# +# Typical Boot sequence (when debugging via JTAG/SWD): +# 1. Load AT91Bootstrap to SRAM (0x00100000) +# - Initializes clocks, DDR, peripherals, disables watchdog +# 2. Load application to DDR (0x60000000) +# - Zephyr, Linux, or bare-metal application +# - DDR must be initialized by AT91Bootstrap first +# +# Reset sources on this board: +# - Power-on reset from MCP16502 PMIC +# - User push button SW2 (Board Reset, connected to NRST) +# - External JTAG/J-Link-OB reset from debug probe +# +# Usage with external probe on J27 (J26 MUST be closed): +# openocd -f interface/jlink.cfg -f board/microchip/sama7g54_ek.cfg +# +# Usage with SWD (external probe): +# openocd -f interface/jlink.cfg -c "transport select swd" \ +# -f board/microchip/sama7g54_ek.cfg + +# Default to JTAG -- silently ignored if already selected +catch { transport select jtag } + +# Target configuration (supports both JTAG and SWD) +source [find target/microchip/sama7g5.cfg] + +# Board-specific adapter speed +# Start at lower speed for reliable initial connection. +# Speed increases to 4 MHz after reset-init event (configured in target file). +adapter speed 1000 + +# Reset configuration for external probe on J27 (J26 closed). +# Both SRST (pin 15/nRST) and TRST (pin 3/NTRST) are available +# on the 20-pin JTAG header. +# NTRST (PC25) has an internal pull-up -- safe to connect. +# +# srst_nogate: SRST is not gated by the JTAG state machine -- +# required because NRST resets the entire chip including debug logic. +# +# For probes with only SRST wired (no TRST), use instead: +# reset_config srst_only srst_nogate +# +reset_config trst_and_srst srst_nogate diff --git a/tcl/target/microchip/sama7g5.cfg b/tcl/target/microchip/sama7g5.cfg new file mode 100644 index 0000000000..411842ab87 --- /dev/null +++ b/tcl/target/microchip/sama7g5.cfg @@ -0,0 +1,175 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# +# Target configuration for Microchip SAMA7G5 series +# +# Cortex-A7 based Microprocessor Unit (MPU) +# https://www.microchip.com/en-us/product/sama7g54 +# Datasheet: DS60001765 +# +# SAMA7G5 series currently includes: +# - SAMA7G54 +# +# Supports both JTAG and SWD transports. +# Select transport before sourcing this file: +# -c "transport select jtag" +# -c "transport select swd" +# If not specified, the adapter driver will auto-select. +# +# IMPORTANT: JTAG/SWD Access Requires ROM Code Completion +# The SAMA7G5 ROM code disables JTAG during boot. +# JTAG is enabled only after one of: +# a) The ROM code finds a valid boot image (e.g., AT91Bootstrap) +# and jumps to SRAM -- JTAG is enabled at that point +# b) No valid NVM found -- ROM code enters SAM-BA Monitor, +# enables USB + UART + JTAG connection +# +# On a blank/fresh board with no NVM programmed: +# - Power on the board +# - Wait for ROM code to enter SAM-BA Monitor +# - JTAG is then enabled automatically +# +# JTAG/Debug Security (OTP Fuses): +# OTPC_UHC0R.JTAGDIS[7:0] = 0x00 (default): JTAG enabled +# OTPC_UHC0R.JTAGDIS[7:0] != 0x00: JTAG permanently disabled +# OTPC_UHC0R.SECDBG[7:0] = 0x00 (default): Secure debug allowed +# OTPC_UHC0R.SECDBG[7:0] != 0x00: Secure debug permanently forbidden +# WARNING: If these OTP fuses are blown, JTAG/SWD is permanently disabled. +# +# Hardware watchdog warning: +# When connecting before AT91Bootstrap runs, the hardware watchdog +# may reset the chip periodically, causing transient DAP errors. +# OpenOCD automatically recovers by re-examining the target. +# The watchdog is disabled by AT91Bootstrap during normal boot. +# + +source [find mem_helper.tcl] + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME sama7g5 +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + set _ENDIAN little +} + +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + # ARM CoreSight JTAG-DP IDCODE + # Version=0x6, Part=0xBA00, Designer=ARM Ltd. + set _CPUTAPID 0x6ba00477 +} + +if { [info exists DAP_TAPID] } { + set _DAP_TAPID $DAP_TAPID +} else { + # ARM CoreSight SW-DP DPIDR + set _DAP_TAPID 0x6ba02477 +} + +# +# JTAG or SWD configuration +# +if { [using_jtag] } { + jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID +} else { + swd newdap $_CHIPNAME cpu -expected-id $_DAP_TAPID +} + +# +# DAP (Debug Access Port) -- required for Cortex-A targets +# +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu + +# +# Target: Cortex-A7 (single core) +# +set _TARGETNAME $_CHIPNAME.cpu.0 +target create $_TARGETNAME cortex_a -dap $_CHIPNAME.dap -endian $_ENDIAN -coreid 0 + +# +# SRAM: 128KB at 0x00100000 +# Used by OpenOCD as work area for flash programming and memory operations. +# +# CAUTION: This SRAM is shared with the ROM code and AT91Bootstrap. +# - During boot: ROM code uses SRAM for bootloader operations +# - After AT91Bootstrap: SRAM contains bootstrap code +# - Set -work-area-backup 1 if you need to preserve SRAM contents +# +$_TARGETNAME configure -work-area-phys 0x00100000 -work-area-size 0x20000 -work-area-backup 0 + +# +# Event handlers +# + +$_TARGETNAME configure -event examine-start { + # Start at conservative speed for reliable initial connection. + adapter speed 1000 +} + +$_TARGETNAME configure -event examine-end { + # Halt CPU immediately to prevent WFI sleep mode + # which can power down debug regions. + # + # Note: This will fail if the ROM code has not yet enabled JTAG. + # JTAG is disabled during ROM code execution and only enabled after: + # - A valid boot image is found and execution jumps to SRAM, OR + # - The SAM-BA Monitor is entered (no valid NVM found) + # Transient errors here are expected and recoverable. + if { [catch { $_TARGETNAME arp_halt }] } { + echo "Warning: Could not halt target." + echo " JTAG may not be enabled yet (ROM code disables it during boot)." + echo " Ensure AT91Bootstrap is flashed, or wait for SAM-BA Monitor entry." + } + catch { $_TARGETNAME arp_waitstate halted 1000 } +} + +$_TARGETNAME configure -event gdb-attach { + # Halt CPU when debugger connects + halt +} + +$_TARGETNAME configure -event gdb-detach { + # Resume CPU when debugger disconnects + resume +} + +$_TARGETNAME configure -event reset-start { + # Reduce speed during reset for stability + adapter speed 1000 +} + +$_TARGETNAME configure -event reset-init { + # Increase speed after reset initialization + adapter speed 4000 +} + +# +# Troubleshooting: +# +# Connection fails immediately after power-on: +# - JTAG is disabled by ROM code during boot +# - On a blank board, wait for SAM-BA Monitor to enable JTAG +# - If AT91Bootstrap is flashed in NVM, JTAG is enabled at SRAM jump +# +# Connection permanently fails: +# - Check OTPC_UHC0R.JTAGDIS fuse -- if non-zero, JTAG is permanently disabled +# - Check OTPC_UHC0R.SECDBG fuse -- if non-zero, secure debug is forbidden +# +# Hardware checks: +# - Ensure JTAGSEL pin is LOW (default with internal pull-down) +# - Ensure TST pin is LOW (must be tied low for normal operation) +# - NTRST (PC25) has internal pull-up (deasserted by default) +# - Verify VDDIN33 power is stable (powers all debug pins PC25-PC29) +# - Use lower adapter speeds (1000 kHz) if experiencing intermittent errors +# - Watchdog resets are normal before AT91Bootstrap disables it +# +# SAM-BA Monitor recovery (when no valid NVM boot image exists): +# - ROM code enters SAM-BA Monitor automatically, enabling JTAG +# - Serial console available at 115200 baud, 8N1 +# - See board configuration file for board-specific USB and UART details +# --
