This is an automated email from Gerrit. "Alexey Charkov <[email protected]>" just uploaded a new patch set to Gerrit, which you can find at https://review.openocd.org/c/openocd/+/9567
-- gerrit commit c5acc2cc6bfae903caca55d8b82f776fe39c53fb Author: Alexey Charkov <[email protected]> Date: Wed Apr 8 13:47:23 2026 +0400 tcl/target: add Rockchip RK3576 target The Rockchip RK3576 SoC is used in a number of SBCs such as the ArmSoM Sige5, FriendlyElec NanoPi M5 and others. Add the target config to debug those over the SWD connection exposed via SDMMC card pins D2 (SWCLK) and D3 (SWDIO). Tested using a custom mini-PCB in the shape of a microSD card with an extra cutout to avoid triggering the card detect switch (which forces the SoC to switch the pins from SWD mode to SD). Change-Id: I2d97058784f5a774fc2cb62baff0cb2a51102fcc Signed-off-by: Alexey Charkov <[email protected]> diff --git a/tcl/target/rk3576.cfg b/tcl/target/rk3576.cfg new file mode 100644 index 0000000000..759d1960c1 --- /dev/null +++ b/tcl/target/rk3576.cfg @@ -0,0 +1,86 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# Rockchip RK3576 Target +# https://www.rock-chips.com/a/en/products/RK35_Series/2024/1212/2033.html +# Alexey Charkov <[email protected]> + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME rk3576 +} + +if { [info exists DAP_TAPID] } { + set _DAP_TAPID $DAP_TAPID +} else { + set _DAP_TAPID 0x2ba01477 +} + +adapter speed 4000 + +transport select swd + +# Declare the one SWD tap to access the DAP +swd newdap $_CHIPNAME cpu -expected-id $_DAP_TAPID + +# Create the DAP +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu + +# Create target to allow accessing system memory directly +target create $_CHIPNAME.ahb mem_ap -dap $_CHIPNAME.dap -ap-num 0 + +# Declare the 8 main application cores (4 little cores + 4 big cores) + +# Little cluster (cores 0..3) +set _TARGETNAME $_CHIPNAME.lcore +set $_TARGETNAME.base(0) 0x81010000 +set $_TARGETNAME.base(1) 0x81012000 +set $_TARGETNAME.base(2) 0x81014000 +set $_TARGETNAME.base(3) 0x81016000 +set $_TARGETNAME.cti(0) 0x81018000 +set $_TARGETNAME.cti(1) 0x81019000 +set $_TARGETNAME.cti(2) 0x8101a000 +set $_TARGETNAME.cti(3) 0x8101b000 + +# Big cluster (cores 4..7) +set _TARGETNAME $_CHIPNAME.bcore +set $_TARGETNAME.base(4) 0x80210000 +set $_TARGETNAME.base(5) 0x80310000 +set $_TARGETNAME.base(6) 0x80410000 +set $_TARGETNAME.base(7) 0x80510000 +set $_TARGETNAME.cti(4) 0x80220000 +set $_TARGETNAME.cti(5) 0x80320000 +set $_TARGETNAME.cti(6) 0x80420000 +set $_TARGETNAME.cti(7) 0x80520000 + +# Build string used to enable SMP mode +set _smp_command "target smp" + +set _cores 8 +for { set _core 0 } { $_core < $_cores } { incr _core 1 } { + if {$_core < 4} { + set _TARGETNAME $_CHIPNAME.lcore + } else { + set _TARGETNAME $_CHIPNAME.bcore + } + + cti create cti$_core -dap $_CHIPNAME.dap -baseaddr [set $_TARGETNAME.cti($_core)] -ap-num 0 + + target create ${_TARGETNAME}$_core aarch64 \ + -dap $_CHIPNAME.dap -coreid $_core -cti cti$_core \ + -dbgbase [set $_TARGETNAME.base($_core)] + + if { $_core != 0 } { + # non-boot core examination may fail + ${_TARGETNAME}$_core configure -defer-examine + } else { + # uncomment to use hardware threads pseudo rtos + # ${_TARGETNAME}$_core configure -rtos hwthread + } + + set _smp_command "$_smp_command ${_TARGETNAME}$_core" +} + +eval $_smp_command + +# Set default target to boot core +targets $_CHIPNAME.lcore0 --
