This is an automated email from Gerrit. "Antonio Borneo <[email protected]>" just uploaded a new patch set to Gerrit, which you can find at https://review.openocd.org/c/openocd/+/9509
-- gerrit commit a13b50c044dd36c8deac3f284f931e211f76bb13 Author: Antonio Borneo <[email protected]> Date: Mon Mar 16 17:38:06 2026 +0100 target: arm: provide specific instruction-set to capstone To deprecate the old command 'arm disassemble', provide a common generic callback armv4_5_insn_set() and add it to all arm target types. Add also support for the "armbe" instruction-set, Change-Id: Iaf56c823119bd0f8bbb8d810dd1ba063a3655e40 Signed-off-by: Antonio Borneo <[email protected]> diff --git a/src/target/arm.h b/src/target/arm.h index 6d6412219e..020b4912a6 100644 --- a/src/target/arm.h +++ b/src/target/arm.h @@ -330,4 +330,7 @@ void arm_set_cpsr(struct arm *arm, uint32_t cpsr); struct reg *arm_reg_current(struct arm *arm, unsigned int regnum); struct reg *armv8_reg_current(struct arm *arm, unsigned int regnum); +int armv4_5_insn_set(struct command_invocation *cmd, struct target *target, + const char **insn_set); + #endif /* OPENOCD_TARGET_ARM_H */ diff --git a/src/target/arm11.c b/src/target/arm11.c index 81026c68c4..1ce19fd2f0 100644 --- a/src/target/arm11.c +++ b/src/target/arm11.c @@ -1370,4 +1370,6 @@ struct target_type arm11_target = { .init_target = arm11_init_target, .deinit_target = arm11_deinit_target, .examine = arm11_examine, + + .insn_set = armv4_5_insn_set, }; diff --git a/src/target/arm720t.c b/src/target/arm720t.c index 3f7686fb74..db0a4d27bf 100644 --- a/src/target/arm720t.c +++ b/src/target/arm720t.c @@ -499,4 +499,6 @@ struct target_type arm720t_target = { .deinit_target = arm720t_deinit_target, .examine = arm7_9_examine, .check_reset = arm7_9_check_reset, + + .insn_set = armv4_5_insn_set, }; diff --git a/src/target/arm7tdmi.c b/src/target/arm7tdmi.c index fea6a3ff2a..e974d01e6a 100644 --- a/src/target/arm7tdmi.c +++ b/src/target/arm7tdmi.c @@ -719,4 +719,6 @@ struct target_type arm7tdmi_target = { .deinit_target = arm7tdmi_deinit_target, .examine = arm7_9_examine, .check_reset = arm7_9_check_reset, + + .insn_set = armv4_5_insn_set, }; diff --git a/src/target/arm920t.c b/src/target/arm920t.c index 441e423054..3821d381b5 100644 --- a/src/target/arm920t.c +++ b/src/target/arm920t.c @@ -1631,4 +1631,6 @@ struct target_type arm920t_target = { .deinit_target = arm920t_deinit_target, .examine = arm7_9_examine, .check_reset = arm7_9_check_reset, + + .insn_set = armv4_5_insn_set, }; diff --git a/src/target/arm926ejs.c b/src/target/arm926ejs.c index 98fe6bf68d..94b0612138 100644 --- a/src/target/arm926ejs.c +++ b/src/target/arm926ejs.c @@ -829,4 +829,6 @@ struct target_type arm926ejs_target = { .read_phys_memory = arm926ejs_read_phys_memory, .write_phys_memory = arm926ejs_write_phys_memory, + + .insn_set = armv4_5_insn_set, }; diff --git a/src/target/arm946e.c b/src/target/arm946e.c index 828e70f4bc..ab0ac44e10 100644 --- a/src/target/arm946e.c +++ b/src/target/arm946e.c @@ -778,4 +778,6 @@ struct target_type arm946e_target = { .deinit_target = arm946e_deinit_target, .examine = arm7_9_examine, .check_reset = arm7_9_check_reset, + + .insn_set = armv4_5_insn_set, }; diff --git a/src/target/arm966e.c b/src/target/arm966e.c index b6bcc8ba97..1203b76880 100644 --- a/src/target/arm966e.c +++ b/src/target/arm966e.c @@ -280,4 +280,6 @@ struct target_type arm966e_target = { .deinit_target = arm966e_deinit_target, .examine = arm7_9_examine, .check_reset = arm7_9_check_reset, + + .insn_set = armv4_5_insn_set, }; diff --git a/src/target/arm9tdmi.c b/src/target/arm9tdmi.c index 34b4ba2cea..f980d91ca3 100644 --- a/src/target/arm9tdmi.c +++ b/src/target/arm9tdmi.c @@ -923,4 +923,6 @@ struct target_type arm9tdmi_target = { .deinit_target = arm9tdmi_deinit_target, .examine = arm7_9_examine, .check_reset = arm7_9_check_reset, + + .insn_set = armv4_5_insn_set, }; diff --git a/src/target/armv4_5.c b/src/target/armv4_5.c index 4f61c58e2d..1cf4e8ff1a 100644 --- a/src/target/armv4_5.c +++ b/src/target/armv4_5.c @@ -1840,3 +1840,35 @@ int arm_init_arch_info(struct target *target, struct arm *arm) return ERROR_OK; } + +int armv4_5_insn_set(struct command_invocation *cmd, struct target *target, + const char **insn_set) +{ + struct arm *arm = target_to_arm(target); + + if (target->state != TARGET_HALTED) { + command_print(cmd, "[%s] not halted", target_name(target)); + return ERROR_TARGET_NOT_HALTED; + } + + switch (arm->core_state) { + case ARM_STATE_ARM: + if (target->endianness == TARGET_BIG_ENDIAN) + *insn_set = "armbe"; + else + *insn_set = "arm"; + break; + + case ARM_STATE_THUMB: + case ARM_STATE_THUMB_EE: + *insn_set = "thumb"; + break; + + default: + command_print(cmd, "[%s] unknown core_state %d", target_name(target), + arm->core_state); + return ERROR_FAIL; + } + + return ERROR_OK; +} diff --git a/src/target/cortex_a.c b/src/target/cortex_a.c index 2efbcce0c9..102a7cabfa 100644 --- a/src/target/cortex_a.c +++ b/src/target/cortex_a.c @@ -3503,6 +3503,8 @@ struct target_type cortexa_target = { .write_phys_memory = cortex_a_write_phys_memory, .mmu = cortex_a_mmu, .virt2phys = cortex_a_virt2phys, + + .insn_set = armv4_5_insn_set, }; static const struct command_registration cortex_r4_exec_command_handlers[] = { @@ -3575,4 +3577,6 @@ struct target_type cortexr4_target = { .init_target = cortex_a_init_target, .examine = cortex_a_examine, .deinit_target = cortex_a_deinit_target, + + .insn_set = armv4_5_insn_set, }; diff --git a/src/target/fa526.c b/src/target/fa526.c index 8afb1f0061..d56238aca1 100644 --- a/src/target/fa526.c +++ b/src/target/fa526.c @@ -385,4 +385,6 @@ struct target_type fa526_target = { .deinit_target = fa526_deinit_target, .examine = arm7_9_examine, .check_reset = arm7_9_check_reset, + + .insn_set = armv4_5_insn_set, }; diff --git a/src/target/feroceon.c b/src/target/feroceon.c index 2bb7c6a3ed..da2da1c0cf 100644 --- a/src/target/feroceon.c +++ b/src/target/feroceon.c @@ -725,6 +725,8 @@ struct target_type feroceon_target = { .init_target = feroceon_init_target, .deinit_target = feroceon_deinit_target, .examine = feroceon_examine, + + .insn_set = armv4_5_insn_set, }; struct target_type dragonite_target = { @@ -763,4 +765,6 @@ struct target_type dragonite_target = { .target_create = dragonite_target_create, .init_target = feroceon_init_target, .examine = feroceon_examine, + + .insn_set = armv4_5_insn_set, }; diff --git a/src/target/oocd_capstone.c b/src/target/oocd_capstone.c index 5475857a62..1c15cce73f 100644 --- a/src/target/oocd_capstone.c +++ b/src/target/oocd_capstone.c @@ -28,6 +28,7 @@ static struct { cs_mode mode; } all_archs[] = { { "arm", CS_ARCH_ARM, CS_MODE_ARM }, + { "armbe", CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_BIG_ENDIAN }, { "arm64", CS_ARCH_ARM64, CS_MODE_LITTLE_ENDIAN }, { "cortexm", CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_THUMB | CS_MODE_MCLASS }, { "thumb", CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_THUMB }, diff --git a/src/target/xscale.c b/src/target/xscale.c index 712db4ee2a..7d7228de91 100644 --- a/src/target/xscale.c +++ b/src/target/xscale.c @@ -3736,5 +3736,7 @@ struct target_type xscale_target = { .deinit_target = xscale_deinit_target, .virt2phys = xscale_virt2phys, - .mmu = xscale_mmu + .mmu = xscale_mmu, + + .insn_set = armv4_5_insn_set, }; --
