This is an automated email from Gerrit. "Antonio Borneo <[email protected]>" just uploaded a new patch set to Gerrit, which you can find at https://review.openocd.org/c/openocd/+/9532
-- gerrit commit 7c4b066d7ffe7f32c756ee758d4ecaf677399ea3 Author: Antonio Borneo <[email protected]> Date: Mon Mar 16 19:19:06 2026 +0100 target: riscv: enable 'disassemble' command Capstone v5.0 adds support for disassembly of riscv, both RV32I and RV64I. As far as I understand only RV32I is supported by current OpenOCD, no RV64I neither RV128I. Let target_type::insn_set() to only report "riscv32" for capstone. Allow capstone 5.0 and above to decode "riscv32" and "riscv64". Change-Id: Ie9d218233aaf94d0867b4aff7d89350dbcd69ff0 Signed-off-by: Antonio Borneo <[email protected]> diff --git a/src/target/oocd_capstone.c b/src/target/oocd_capstone.c index 6479605fc9..caa0d6ef15 100644 --- a/src/target/oocd_capstone.c +++ b/src/target/oocd_capstone.c @@ -33,6 +33,11 @@ static struct { { "arm64be", CS_ARCH_ARM64, CS_MODE_BIG_ENDIAN }, { "cortexm", CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_THUMB | CS_MODE_MCLASS }, { "thumb", CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_THUMB }, + +#if CS_API_MAJOR >= 5 + { "riscv32", CS_ARCH_RISCV, CS_MODE_RISCV32 | CS_MODE_RISCVC }, + { "riscv64", CS_ARCH_RISCV, CS_MODE_RISCV64 | CS_MODE_RISCVC }, +#endif /* CS_API_MAJOR >= 5 */ }; int oocd_cs_list_insn_types(struct command_invocation *cmd) diff --git a/src/target/riscv/riscv.c b/src/target/riscv/riscv.c index 8054a1c9b7..11aeecbd06 100644 --- a/src/target/riscv/riscv.c +++ b/src/target/riscv/riscv.c @@ -5889,6 +5889,16 @@ static unsigned int riscv_data_bits(struct target *target) return riscv_xlen(target); } +static int riscv_insn_set(struct command_invocation *cmd, + struct target *target, const char **insn_set) +{ + // string match in target/oocd_capstone.c + // As far as I know, only RV32I is currently supported, no RV64I + *insn_set = "riscv32"; + + return ERROR_OK; +} + struct target_type riscv_target = { .name = "riscv", @@ -5936,7 +5946,9 @@ struct target_type riscv_target = { .commands = riscv_command_handlers, .address_bits = riscv_xlen_nonconst, - .data_bits = riscv_data_bits + .data_bits = riscv_data_bits, + + .insn_set = riscv_insn_set, }; /*** RISC-V Interface ***/ --
