This also changes .try_alter() to try_update(). After this commit, instead of "read, write and alter", the methods available for registers are now "read, write and update".
This reads a lot easier for people who are used to working with registers. No functional changes are intended. Signed-off-by: John Hubbard <[email protected]> --- drivers/gpu/nova-core/falcon.rs | 8 ++++---- drivers/gpu/nova-core/regs/macros.rs | 28 ++++++++++++++-------------- 2 files changed, 18 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/nova-core/falcon.rs b/drivers/gpu/nova-core/falcon.rs index 3f505b870601..1e70e39c9671 100644 --- a/drivers/gpu/nova-core/falcon.rs +++ b/drivers/gpu/nova-core/falcon.rs @@ -420,13 +420,13 @@ fn reset_eng(&self, bar: &Bar0) -> Result { } }); - regs::NV_PFALCON_FALCON_ENGINE::alter(bar, &E::ID, |v| v.set_reset(true)); + regs::NV_PFALCON_FALCON_ENGINE::update(bar, &E::ID, |v| v.set_reset(true)); // TODO[DLAY]: replace with udelay() or equivalent once available. // TIMEOUT: falcon engine should not take more than 10us to reset. let _: Result = util::wait_on(Delta::from_micros(10), || None); - regs::NV_PFALCON_FALCON_ENGINE::alter(bar, &E::ID, |v| v.set_reset(false)); + regs::NV_PFALCON_FALCON_ENGINE::update(bar, &E::ID, |v| v.set_reset(false)); self.reset_wait_mem_scrubbing(bar)?; @@ -543,9 +543,9 @@ fn dma_wr<F: FalconFirmware<Target = E>>( /// Perform a DMA load into `IMEM` and `DMEM` of `fw`, and prepare the falcon to run it. pub(crate) fn dma_load<F: FalconFirmware<Target = E>>(&self, bar: &Bar0, fw: &F) -> Result { - regs::NV_PFALCON_FBIF_CTL::alter(bar, &E::ID, |v| v.set_allow_phys_no_ctx(true)); + regs::NV_PFALCON_FBIF_CTL::update(bar, &E::ID, |v| v.set_allow_phys_no_ctx(true)); regs::NV_PFALCON_FALCON_DMACTL::default().write(bar, &E::ID); - regs::NV_PFALCON_FBIF_TRANSCFG::alter(bar, &E::ID, 0, |v| { + regs::NV_PFALCON_FBIF_TRANSCFG::update(bar, &E::ID, 0, |v| { v.set_target(FalconFbifTarget::CoherentSysmem) .set_mem_type(FalconFbifMemType::Physical) }); diff --git a/drivers/gpu/nova-core/regs/macros.rs b/drivers/gpu/nova-core/regs/macros.rs index c0a5194e8d97..fd1a815fa57d 100644 --- a/drivers/gpu/nova-core/regs/macros.rs +++ b/drivers/gpu/nova-core/regs/macros.rs @@ -52,7 +52,7 @@ pub(crate) trait RegisterBase<T> { /// boot0.set_major_revision(3).set_minor_revision(10).write(&bar); /// /// // Or, just read and update the register in a single step: -/// BOOT_0::alter(&bar, |r| r.set_major_revision(3).set_minor_revision(10)); +/// BOOT_0::update(&bar, |r| r.set_major_revision(3).set_minor_revision(10)); /// ``` /// /// The documentation strings are optional. If present, they will be added to the type's @@ -136,15 +136,15 @@ pub(crate) trait RegisterBase<T> { /// 0:0 start as bool, "Start the CPU core"; /// }); /// -/// // The `read`, `write` and `alter` methods of relative registers take an extra `base` argument +/// // The `read`, `write` and `update` methods of relative registers take an extra `base` argument /// // that is used to resolve its final address by adding its `BASE` to the offset of the /// // register. /// /// // Start `CPU0`. -/// CPU_CTL::alter(bar, &CPU0, |r| r.set_start(true)); +/// CPU_CTL::update(bar, &CPU0, |r| r.set_start(true)); /// /// // Start `CPU1`. -/// CPU_CTL::alter(bar, &CPU1, |r| r.set_start(true)); +/// CPU_CTL::update(bar, &CPU1, |r| r.set_start(true)); /// /// // Aliases can also be defined for relative register. /// register!(CPU_CTL_ALIAS => CpuCtlBase[CPU_CTL], "Alias to CPU core control" { @@ -152,7 +152,7 @@ pub(crate) trait RegisterBase<T> { /// }); /// /// // Start the aliased `CPU0`. -/// CPU_CTL_ALIAS::alter(bar, &CPU0, |r| r.set_alias_start(true)); +/// CPU_CTL_ALIAS::update(bar, &CPU0, |r| r.set_alias_start(true)); /// ``` /// /// ## Arrays of registers @@ -160,7 +160,7 @@ pub(crate) trait RegisterBase<T> { /// Some I/O areas contain consecutive values that can be interpreted in the same way. These areas /// can be defined as an array of identical registers, allowing them to be accessed by index with /// compile-time or runtime bound checking. Simply define their address as `Address[Size]`, and add -/// an `idx` parameter to their `read`, `write` and `alter` methods: +/// an `idx` parameter to their `read`, `write` and `update` methods: /// /// ```no_run /// # fn no_run() -> Result<(), Error> { @@ -386,7 +386,7 @@ pub(crate) fn write<const SIZE: usize, T>(self, io: &T) where /// Read the register from its address in `io` and run `f` on its value to obtain a new /// value to write back. #[inline(always)] - pub(crate) fn alter<const SIZE: usize, T, F>( + pub(crate) fn update<const SIZE: usize, T, F>( io: &T, f: F, ) where @@ -449,7 +449,7 @@ pub(crate) fn write<const SIZE: usize, T, B>( /// the register's offset to it, then run `f` on its value to obtain a new value to /// write back. #[inline(always)] - pub(crate) fn alter<const SIZE: usize, T, B, F>( + pub(crate) fn update<const SIZE: usize, T, B, F>( io: &T, base: &B, f: F, @@ -507,7 +507,7 @@ pub(crate) fn write<const SIZE: usize, T>( /// Read the array register at index `idx` in `io` and run `f` on its value to obtain a /// new value to write back. #[inline(always)] - pub(crate) fn alter<const SIZE: usize, T, F>( + pub(crate) fn update<const SIZE: usize, T, F>( io: &T, idx: usize, f: F, @@ -562,7 +562,7 @@ pub(crate) fn try_write<const SIZE: usize, T>( /// The validity of `idx` is checked at run-time, and `EINVAL` is returned is the /// access was out-of-bounds. #[inline(always)] - pub(crate) fn try_alter<const SIZE: usize, T, F>( + pub(crate) fn try_update<const SIZE: usize, T, F>( io: &T, idx: usize, f: F, @@ -571,7 +571,7 @@ pub(crate) fn try_alter<const SIZE: usize, T, F>( F: ::core::ops::FnOnce(Self) -> Self, { if idx < Self::SIZE { - Ok(Self::alter(io, idx, f)) + Ok(Self::update(io, idx, f)) } else { Err(EINVAL) } @@ -636,7 +636,7 @@ pub(crate) fn write<const SIZE: usize, T, B>( /// by `base` and adding the register's offset to it, then run `f` on its value to /// obtain a new value to write back. #[inline(always)] - pub(crate) fn alter<const SIZE: usize, T, B, F>( + pub(crate) fn update<const SIZE: usize, T, B, F>( io: &T, base: &B, idx: usize, @@ -700,7 +700,7 @@ pub(crate) fn try_write<const SIZE: usize, T, B>( /// The validity of `idx` is checked at run-time, and `EINVAL` is returned is the /// access was out-of-bounds. #[inline(always)] - pub(crate) fn try_alter<const SIZE: usize, T, B, F>( + pub(crate) fn try_update<const SIZE: usize, T, B, F>( io: &T, base: &B, idx: usize, @@ -711,7 +711,7 @@ pub(crate) fn try_alter<const SIZE: usize, T, B, F>( F: ::core::ops::FnOnce(Self) -> Self, { if idx < Self::SIZE { - Ok(Self::alter(io, base, idx, f)) + Ok(Self::update(io, base, idx, f)) } else { Err(EINVAL) } -- 2.51.1
