From: Iyappan Subramanian <isubraman...@apm.com>
Date: Mon, 26 Oct 2015 15:25:14 -0700
> X-Gene RGMII ethernet controller has a RGMII bridge that performs the
> task of converting the RGMII signal {RX_CLK,RX_CTL, RX_DATA[3:0]} from
> PHY to GMII signal {RX_DV,RX_ER,RX_DATA[7:0]} and vice versa. This
> RGMII bridge has a provision to internally delay the input RX_CLK and
> the output TX_CLK using configuration registers. This will help in
> maintain the CLK-CTL delay relationship in various operating
> conditions.
>
> This patch adds support RGMII TX/RX delay configuration.
>
> Signed-off-by: Iyappan Subramanian <isubraman...@apm.com>
Series applied, thanks.
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