On Thu, Mar 25, 2021 at 03:34, Vladimir Oltean <olte...@gmail.com> wrote: > On Wed, Mar 24, 2021 at 05:07:09PM +0100, Tobias Waldekranz wrote: >> But even if the parser was enabled, it would never get anywhere since >> the Ethertype would look like random garbage. Unless we have the soft >> parser, but then it is not the middle ground anymore :) > > Garbage, true, but garbage with enough entropy to allow for some sort of > RFS (ideally you can get the source port field from the DSA tag into the > area covered by the n-tuple on which the master performs hashing). This > is the way in which the switches inside NXP LS1028A and T1040 work.
I see what you are saying. Any given flow would still have the same not-really-an-Ethertype. >> I suppose you would like to test for netdev_uses_dsa_and_violates_8023, >> that way you could still do RSS on DSA devices using regular 1Q-tags for >> example. Do we want to add this property to the taggers so that we do >> not degrade performance for any existing users? > > Yes, so T1040 is one such example of device that would be negatively > affected by this change. There isn't a good solution to solve all > problems: there will be some Marvell switches which can't operate in > EDSA mode, and there will be some DSA masters that can't parse Marvell > DSA tags. Eventually all possible combinations of workarounds will have > to be implemented. But for now, I think I prefer to see the simplest > one, which has just become the one based on device tree. Alright, it seems like everyone agrees then. I will look into it. Just to avoid a DenverCoder9 situation; I tried changing the NIA in FMBM_RFNE like you suggested: 8< --- diff --git a/drivers/net/ethernet/freescale/fman/fman_port.c b/drivers/net/ethernet/freescale/fman/fman_port.c index d9baac0dbc7d..5aa5b4068f2d 100644 --- a/drivers/net/ethernet/freescale/fman/fman_port.c +++ b/drivers/net/ethernet/freescale/fman/fman_port.c @@ -543,7 +543,7 @@ static int init_bmi_rx(struct fman_port *port) /* NIA */ tmp = (u32)cfg->rx_fd_bits << BMI_NEXT_ENG_FD_BITS_SHIFT; - tmp |= NIA_ENG_HWP; + tmp |= NIA_ENG_BMI | NIA_BMI_AC_ENQ_FRAME; iowrite32be(tmp, ®s->fmbm_rfne); /* Parser Next Engine NIA */ 8< --- >From what I can tell, this works as expected. TO_CPUs from port 8 can ingress the device with this in place.