On 2/22/2021 3:18 PM, Vladimir Oltean wrote:
> On Mon, Feb 22, 2021 at 02:30:10PM -0800, Florian Fainelli wrote:
>> diff --git a/drivers/net/dsa/b53/b53_regs.h b/drivers/net/dsa/b53/b53_regs.h
>> index c90985c294a2..b2c539a42154 100644
>> --- a/drivers/net/dsa/b53/b53_regs.h
>> +++ b/drivers/net/dsa/b53/b53_regs.h
>> @@ -115,6 +115,7 @@
>> #define B53_UC_FLOOD_MASK 0x32
>> #define B53_MC_FLOOD_MASK 0x34
>> #define B53_IPMC_FLOOD_MASK 0x36
>> +#define B53_DIS_LEARNING 0x3c
>>
>> /*
>> * Override Ports 0-7 State on devices with xMII interfaces (8 bit)
>> diff --git a/drivers/net/dsa/bcm_sf2.c b/drivers/net/dsa/bcm_sf2.c
>> index 3eaedbb12815..5ee8103b8e9c 100644
>> --- a/drivers/net/dsa/bcm_sf2.c
>> +++ b/drivers/net/dsa/bcm_sf2.c
>> @@ -223,23 +223,10 @@ static int bcm_sf2_port_setup(struct dsa_switch *ds,
>> int port,
>> reg &= ~P_TXQ_PSM_VDD(port);
>> core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);
>>
>> - /* Enable learning */
>> - reg = core_readl(priv, CORE_DIS_LEARN);
>> - reg &= ~BIT(port);
>> - core_writel(priv, reg, CORE_DIS_LEARN);
>> -
>> /* Enable Broadcom tags for that port if requested */
>> - if (priv->brcm_tag_mask & BIT(port)) {
>> + if (priv->brcm_tag_mask & BIT(port))
>> b53_brcm_hdr_setup(ds, port);
>>
>> - /* Disable learning on ASP port */
>> - if (port == 7) {
>> - reg = core_readl(priv, CORE_DIS_LEARN);
>> - reg |= BIT(port);
>> - core_writel(priv, reg, CORE_DIS_LEARN);
>> - }
>> - }
>> -
>
> In sf2, CORE_DIS_LEARN is at address 0xf0, while in b53, B53_DIS_LEARN
> is at 0x3c. Are they even configuring the same thing?
They are the SF2 switch was integrated with a bridge that would flatten
its address space such that there would be no need to access the
registers indirectly like what b53_srab does.
This is the reason why we have the SF2_PAGE_REG_MKADDR() macro to
convert from a {page, offset} tuple to a memory mapped address and here
0x3c << 2 = 0xf0.
--
Florian
