From: Yevgeny Kliteynik <klit...@nvidia.com>
Fix 32-bit variable shift wrapping in dr_ste_v0_get_miss_addr.
Fixes: 6b93b400aa88 ("net/mlx5: DR, Move STEv0 setters and getters")
Reported-by: Dan Carpenter <dan.carpen...@oracle.com>
Signed-off-by: Yevgeny Kliteynik <klit...@nvidia.com>
Reviewed-by: Alex Vesker <va...@nvidia.com>
Signed-off-by: Saeed Mahameed <sae...@nvidia.com>
---
drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste_v0.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste_v0.c
b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste_v0.c
index b76fdff08890..9ec079247c4b 100644
--- a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste_v0.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste_v0.c
@@ -248,8 +248,8 @@ static void dr_ste_v0_set_miss_addr(u8 *hw_ste_p, u64
miss_addr)
static u64 dr_ste_v0_get_miss_addr(u8 *hw_ste_p)
{
u64 index =
- (MLX5_GET(ste_rx_steering_mult, hw_ste_p, miss_address_31_6) |
- MLX5_GET(ste_rx_steering_mult, hw_ste_p, miss_address_39_32)
<< 26);
+ ((u64)MLX5_GET(ste_rx_steering_mult, hw_ste_p,
miss_address_31_6) |
+ ((u64)MLX5_GET(ste_rx_steering_mult, hw_ste_p,
miss_address_39_32)) << 26);
return index << 6;
}
--
2.29.2
