On Fri, 22 Jan 2021 16:13:47 +0100 Laurent Badel wrote:
> fec_restart() does a hard reset of the MAC module when the link status
> changes to up. This temporarily resets the R_CNTRL register which controls
> the MII mode of the ENET_OUT clock. In the case of RMII, the clock
> frequency momentarily drops from 50MHz to 25MHz until the register is
> reconfigured. Some link partners do not tolerate this glitch and
> invalidate the link causing failure to establish a stable link when using
> PHY polling mode. Since as per IEEE802.11 the criteria for link validity
> are PHY-specific, what the partner should tolerate cannot be assumed, so
> avoid resetting the MII clock by using software reset instead of hardware
> reset when the link is up. This is generally relevant only if the SoC
> provides the clock to an external PHY and the PHY is configured for RMII.
> static const struct fec_devinfo fec_imx6q_info = {
> @@ -953,7 +954,8 @@ fec_restart(struct net_device *ndev)
> * For i.MX6SX SOC, enet use AXI bus, we use disable MAC
> * instead of reset MAC itself.
> */
> - if (fep->quirks & FEC_QUIRK_HAS_AVB) {
> + if (fep->quirks & FEC_QUIRK_HAS_AVB ||
> + (fep->quirks & FEC_QUIRK_NO_HARD_RESET) && fep->link) {
> writel(0, fep->hwp + FEC_ECNTRL);
> } else {
> writel(1, fep->hwp + FEC_ECNTRL);
drivers/net/ethernet/freescale/fec_main.c: In function ‘fec_restart’:
drivers/net/ethernet/freescale/fec_main.c:958:46: warning: suggest parentheses
around ‘&&’ within ‘||’ [-Wparentheses]
958 | (fep->quirks & FEC_QUIRK_NO_HARD_RESET) && fep->link) {
| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~
