On 1/20/2021 6:36 PM, Vladimir Oltean wrote:
> From: Vladimir Oltean <vladimir.olt...@nxp.com>
>
> There are use cases for which the existing tagger, based on the NPI
> (Node Processor Interface) functionality, is insufficient.
>
> Namely:
> - Frames injected through the NPI port bypass the frame analyzer, so no
> source address learning is performed, no TSN stream classification,
> etc.
> - Flow control is not functional over an NPI port (PAUSE frames are
> encapsulated in the same Extraction Frame Header as all other frames)
> - There can be at most one NPI port configured for an Ocelot switch. But
> in NXP LS1028A and T1040 there are two Ethernet CPU ports. The non-NPI
> port is currently either disabled, or operated as a plain user port
> (albeit an internally-facing one). Having the ability to configure the
> two CPU ports symmetrically could pave the way for e.g. creating a LAG
> between them, to increase bandwidth seamlessly for the system.
>
> So there is a desire to have an alternative to the NPI mode. This change
> keeps the default tagger for the Seville and Felix switches as "ocelot",
> but it can be changed via the following device attribute:
>
> echo ocelot-8021q > /sys/class/<dsa-master>/dsa/tagging
>
> Signed-off-by: Vladimir Oltean <vladimir.olt...@nxp.com>
Reviewed-by: Florian Fainelli <f.faine...@gmail.com>
--
Florian
