On Mon, Jan 04, 2021 at 09:22:17AM +0100, Steen Hegelund wrote:
> Add the Microchip Sparx5 ethernet serdes PHY driver for the 6G, 10G and 25G
> interfaces available in the Sparx5 SoC.
>
> Signed-off-by: Bjarni Jonasson <bjarni.jonas...@microchip.com>
> Signed-off-by: Steen Hegelund <steen.hegel...@microchip.com>
> Reviewed-by: Andrew Lunn <and...@lunn.ch>
> ---
> drivers/phy/Kconfig | 1 +
> drivers/phy/Makefile | 1 +
> drivers/phy/microchip/Kconfig | 12 +
> drivers/phy/microchip/Makefile | 6 +
> drivers/phy/microchip/sparx5_serdes.c | 2443 ++++++++++++++++++
> drivers/phy/microchip/sparx5_serdes.h | 129 +
> drivers/phy/microchip/sparx5_serdes_regs.h | 2695 ++++++++++++++++++++
> 7 files changed, 5287 insertions(+)
> create mode 100644 drivers/phy/microchip/Kconfig
> create mode 100644 drivers/phy/microchip/Makefile
> create mode 100644 drivers/phy/microchip/sparx5_serdes.c
> create mode 100644 drivers/phy/microchip/sparx5_serdes.h
> create mode 100644 drivers/phy/microchip/sparx5_serdes_regs.h
>
> diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
> index 00dabe5fab8a..df35c752f3aa 100644
> --- a/drivers/phy/Kconfig
> +++ b/drivers/phy/Kconfig
> @@ -70,6 +70,7 @@ source "drivers/phy/ingenic/Kconfig"
> source "drivers/phy/lantiq/Kconfig"
> source "drivers/phy/marvell/Kconfig"
> source "drivers/phy/mediatek/Kconfig"
> +source "drivers/phy/microchip/Kconfig"
> source "drivers/phy/motorola/Kconfig"
> source "drivers/phy/mscc/Kconfig"
> source "drivers/phy/qualcomm/Kconfig"
> diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
> index 32261e164abd..adac1b1a39d1 100644
> --- a/drivers/phy/Makefile
> +++ b/drivers/phy/Makefile
> @@ -20,6 +20,7 @@ obj-y += allwinner/
> \
> lantiq/ \
> marvell/ \
> mediatek/ \
> + microchip/ \
> motorola/ \
> mscc/ \
> qualcomm/ \
> diff --git a/drivers/phy/microchip/Kconfig b/drivers/phy/microchip/Kconfig
> new file mode 100644
> index 000000000000..0b1a818e01b8
<...>
> +struct sparx5_sd10g28_args {
> + bool skip_cmu_cfg; /* Enable/disable CMU cfg */
> + bool no_pwrcycle; /* Omit initial power-cycle */
> + bool txinvert; /* Enable inversion of output data */
> + bool rxinvert; /* Enable inversion of input data */
> + bool txmargin; /* Set output level to half/full */
> + u16 txswing; /* Set output level */
> + bool mute; /* Mute Output Buffer */
> + bool is_6g;
> + bool reg_rst;
> +};
All those bools in structs can be squeezed into one u8, just use
bitfields, e.g. "u8 a:1;".
Also I strongly advise do not do vertical alignment, it will cause to
too many churn later when this code will be updated.
> +
<...>
> +static inline void __iomem *sdx5_addr(void __iomem *base[],
> + int id, int tinst, int tcnt,
> + int gbase, int ginst,
> + int gcnt, int gwidth,
> + int raddr, int rinst,
> + int rcnt, int rwidth)
> +{
> +#if defined(CONFIG_DEBUG_KERNEL)
> + WARN_ON((tinst) >= tcnt);
> + WARN_ON((ginst) >= gcnt);
> + WARN_ON((rinst) >= rcnt);
> +#endif
Please don't put "#if defined(CONFIG_DEBUG_KERNEL)", print WARN_ON().
Thanks
