Hi David, On Wed, Nov 11, 2020 at 2:52 PM David Laight <david.lai...@aculab.com> wrote:
> I've seen a 'fec' ethernet block in a freescale DSP. > IIRC it is a fairly simple block - won't be doing out-of-order writes. > > The imx6q seems to be arm based. This is correct. > I'm guessing that means it doesn't do cache coherency for ethernet dma > accesses. > That (more or less) means the rings need to be mapped uncached. > Any attempt to just flush/invalidate the cache lines is doomed. This is the driver: drivers/net/ethernet/freescale/fec_main.c
